// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
// Date        : Thu Jun 20 02:35:17 2024
// Host        : lsin-ThinkStation-K-C2490 running 64-bit Ubuntu 23.10
// Command     : write_verilog -force -mode funcsim
//               /home/lsin/vivado_projects/lab2rev/part4/part3.gen/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0_sim_netlist.v
// Design      : design_1_auto_ds_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xczu5eg-sfvc784-1-e
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "design_1_auto_ds_0,axi_dwidth_converter_v2_1_29_top,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_dwidth_converter_v2_1_29_top,Vivado 2023.2" *) 
(* NotValidForBitStream *)
module design_1_auto_ds_0
   (s_axi_aclk,
    s_axi_aresetn,
    s_axi_awid,
    s_axi_awaddr,
    s_axi_awlen,
    s_axi_awsize,
    s_axi_awburst,
    s_axi_awlock,
    s_axi_awcache,
    s_axi_awprot,
    s_axi_awregion,
    s_axi_awqos,
    s_axi_awvalid,
    s_axi_awready,
    s_axi_wdata,
    s_axi_wstrb,
    s_axi_wlast,
    s_axi_wvalid,
    s_axi_wready,
    s_axi_bid,
    s_axi_bresp,
    s_axi_bvalid,
    s_axi_bready,
    s_axi_arid,
    s_axi_araddr,
    s_axi_arlen,
    s_axi_arsize,
    s_axi_arburst,
    s_axi_arlock,
    s_axi_arcache,
    s_axi_arprot,
    s_axi_arregion,
    s_axi_arqos,
    s_axi_arvalid,
    s_axi_arready,
    s_axi_rid,
    s_axi_rdata,
    s_axi_rresp,
    s_axi_rlast,
    s_axi_rvalid,
    s_axi_rready,
    m_axi_awaddr,
    m_axi_awlen,
    m_axi_awsize,
    m_axi_awburst,
    m_axi_awlock,
    m_axi_awcache,
    m_axi_awprot,
    m_axi_awregion,
    m_axi_awqos,
    m_axi_awvalid,
    m_axi_awready,
    m_axi_wdata,
    m_axi_wstrb,
    m_axi_wlast,
    m_axi_wvalid,
    m_axi_wready,
    m_axi_bresp,
    m_axi_bvalid,
    m_axi_bready,
    m_axi_araddr,
    m_axi_arlen,
    m_axi_arsize,
    m_axi_arburst,
    m_axi_arlock,
    m_axi_arcache,
    m_axi_arprot,
    m_axi_arregion,
    m_axi_arqos,
    m_axi_arvalid,
    m_axi_arready,
    m_axi_rdata,
    m_axi_rresp,
    m_axi_rlast,
    m_axi_rvalid,
    m_axi_rready);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN, INSERT_VIP 0" *) input s_axi_aclk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input s_axi_aresetn;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [15:0]s_axi_awid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [39:0]s_axi_awaddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [127:0]s_axi_wdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [15:0]s_axi_wstrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [15:0]s_axi_bid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [15:0]s_axi_arid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [39:0]s_axi_araddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [15:0]s_axi_rid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [127:0]s_axi_rdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 16, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input s_axi_rready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [39:0]m_axi_awaddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [7:0]m_axi_awlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]m_axi_awsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output [1:0]m_axi_awburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output [0:0]m_axi_awlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output [3:0]m_axi_awcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *) output [3:0]m_axi_awregion;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output [3:0]m_axi_awqos;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output m_axi_wlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [39:0]m_axi_araddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [7:0]m_axi_arlen;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]m_axi_arsize;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]m_axi_arburst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output [0:0]m_axi_arlock;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]m_axi_arcache;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) output [3:0]m_axi_arregion;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output [3:0]m_axi_arqos;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 40, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready;

  wire [39:0]m_axi_araddr;
  wire [1:0]m_axi_arburst;
  wire [3:0]m_axi_arcache;
  wire [7:0]m_axi_arlen;
  wire [0:0]m_axi_arlock;
  wire [2:0]m_axi_arprot;
  wire [3:0]m_axi_arqos;
  wire m_axi_arready;
  wire [3:0]m_axi_arregion;
  wire [2:0]m_axi_arsize;
  wire m_axi_arvalid;
  wire [39:0]m_axi_awaddr;
  wire [1:0]m_axi_awburst;
  wire [3:0]m_axi_awcache;
  wire [7:0]m_axi_awlen;
  wire [0:0]m_axi_awlock;
  wire [2:0]m_axi_awprot;
  wire [3:0]m_axi_awqos;
  wire m_axi_awready;
  wire [3:0]m_axi_awregion;
  wire [2:0]m_axi_awsize;
  wire m_axi_awvalid;
  wire m_axi_bready;
  wire [1:0]m_axi_bresp;
  wire m_axi_bvalid;
  wire [31:0]m_axi_rdata;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire [1:0]m_axi_rresp;
  wire m_axi_rvalid;
  wire [31:0]m_axi_wdata;
  wire m_axi_wlast;
  wire m_axi_wready;
  wire [3:0]m_axi_wstrb;
  wire m_axi_wvalid;
  wire s_axi_aclk;
  wire [39:0]s_axi_araddr;
  wire [1:0]s_axi_arburst;
  wire [3:0]s_axi_arcache;
  wire s_axi_aresetn;
  wire [15:0]s_axi_arid;
  wire [7:0]s_axi_arlen;
  wire [0:0]s_axi_arlock;
  wire [2:0]s_axi_arprot;
  wire [3:0]s_axi_arqos;
  wire s_axi_arready;
  wire [3:0]s_axi_arregion;
  wire [2:0]s_axi_arsize;
  wire s_axi_arvalid;
  wire [39:0]s_axi_awaddr;
  wire [1:0]s_axi_awburst;
  wire [3:0]s_axi_awcache;
  wire [15:0]s_axi_awid;
  wire [7:0]s_axi_awlen;
  wire [0:0]s_axi_awlock;
  wire [2:0]s_axi_awprot;
  wire [3:0]s_axi_awqos;
  wire s_axi_awready;
  wire [3:0]s_axi_awregion;
  wire [2:0]s_axi_awsize;
  wire s_axi_awvalid;
  wire [15:0]s_axi_bid;
  wire s_axi_bready;
  wire [1:0]s_axi_bresp;
  wire s_axi_bvalid;
  wire [127:0]s_axi_rdata;
  wire [15:0]s_axi_rid;
  wire s_axi_rlast;
  wire s_axi_rready;
  wire [1:0]s_axi_rresp;
  wire s_axi_rvalid;
  wire [127:0]s_axi_wdata;
  wire s_axi_wready;
  wire [15:0]s_axi_wstrb;
  wire s_axi_wvalid;

  (* C_AXI_ADDR_WIDTH = "40" *) 
  (* C_AXI_IS_ACLK_ASYNC = "0" *) 
  (* C_AXI_PROTOCOL = "0" *) 
  (* C_AXI_SUPPORTS_READ = "1" *) 
  (* C_AXI_SUPPORTS_WRITE = "1" *) 
  (* C_FAMILY = "zynquplus" *) 
  (* C_FIFO_MODE = "0" *) 
  (* C_MAX_SPLIT_BEATS = "256" *) 
  (* C_M_AXI_ACLK_RATIO = "2" *) 
  (* C_M_AXI_BYTES_LOG = "2" *) 
  (* C_M_AXI_DATA_WIDTH = "32" *) 
  (* C_PACKING_LEVEL = "1" *) 
  (* C_RATIO = "4" *) 
  (* C_RATIO_LOG = "2" *) 
  (* C_SUPPORTS_ID = "1" *) 
  (* C_SYNCHRONIZER_STAGE = "3" *) 
  (* C_S_AXI_ACLK_RATIO = "1" *) 
  (* C_S_AXI_BYTES_LOG = "4" *) 
  (* C_S_AXI_DATA_WIDTH = "128" *) 
  (* C_S_AXI_ID_WIDTH = "16" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* P_AXI3 = "1" *) 
  (* P_AXI4 = "0" *) 
  (* P_AXILITE = "2" *) 
  (* P_CONVERSION = "2" *) 
  (* P_MAX_SPLIT_BEATS = "256" *) 
  design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_top inst
       (.m_axi_aclk(1'b0),
        .m_axi_araddr(m_axi_araddr),
        .m_axi_arburst(m_axi_arburst),
        .m_axi_arcache(m_axi_arcache),
        .m_axi_aresetn(1'b0),
        .m_axi_arlen(m_axi_arlen),
        .m_axi_arlock(m_axi_arlock),
        .m_axi_arprot(m_axi_arprot),
        .m_axi_arqos(m_axi_arqos),
        .m_axi_arready(m_axi_arready),
        .m_axi_arregion(m_axi_arregion),
        .m_axi_arsize(m_axi_arsize),
        .m_axi_arvalid(m_axi_arvalid),
        .m_axi_awaddr(m_axi_awaddr),
        .m_axi_awburst(m_axi_awburst),
        .m_axi_awcache(m_axi_awcache),
        .m_axi_awlen(m_axi_awlen),
        .m_axi_awlock(m_axi_awlock),
        .m_axi_awprot(m_axi_awprot),
        .m_axi_awqos(m_axi_awqos),
        .m_axi_awready(m_axi_awready),
        .m_axi_awregion(m_axi_awregion),
        .m_axi_awsize(m_axi_awsize),
        .m_axi_awvalid(m_axi_awvalid),
        .m_axi_bready(m_axi_bready),
        .m_axi_bresp(m_axi_bresp),
        .m_axi_bvalid(m_axi_bvalid),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rresp(m_axi_rresp),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_wdata(m_axi_wdata),
        .m_axi_wlast(m_axi_wlast),
        .m_axi_wready(m_axi_wready),
        .m_axi_wstrb(m_axi_wstrb),
        .m_axi_wvalid(m_axi_wvalid),
        .s_axi_aclk(s_axi_aclk),
        .s_axi_araddr(s_axi_araddr),
        .s_axi_arburst(s_axi_arburst),
        .s_axi_arcache(s_axi_arcache),
        .s_axi_aresetn(s_axi_aresetn),
        .s_axi_arid(s_axi_arid),
        .s_axi_arlen(s_axi_arlen),
        .s_axi_arlock(s_axi_arlock),
        .s_axi_arprot(s_axi_arprot),
        .s_axi_arqos(s_axi_arqos),
        .s_axi_arready(s_axi_arready),
        .s_axi_arregion(s_axi_arregion),
        .s_axi_arsize(s_axi_arsize),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_awaddr(s_axi_awaddr),
        .s_axi_awburst(s_axi_awburst),
        .s_axi_awcache(s_axi_awcache),
        .s_axi_awid(s_axi_awid),
        .s_axi_awlen(s_axi_awlen),
        .s_axi_awlock(s_axi_awlock),
        .s_axi_awprot(s_axi_awprot),
        .s_axi_awqos(s_axi_awqos),
        .s_axi_awready(s_axi_awready),
        .s_axi_awregion(s_axi_awregion),
        .s_axi_awsize(s_axi_awsize),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_bid(s_axi_bid),
        .s_axi_bready(s_axi_bready),
        .s_axi_bresp(s_axi_bresp),
        .s_axi_bvalid(s_axi_bvalid),
        .s_axi_rdata(s_axi_rdata),
        .s_axi_rid(s_axi_rid),
        .s_axi_rlast(s_axi_rlast),
        .s_axi_rready(s_axi_rready),
        .s_axi_rresp(s_axi_rresp),
        .s_axi_rvalid(s_axi_rvalid),
        .s_axi_wdata(s_axi_wdata),
        .s_axi_wlast(1'b0),
        .s_axi_wready(s_axi_wready),
        .s_axi_wstrb(s_axi_wstrb),
        .s_axi_wvalid(s_axi_wvalid));
endmodule

(* ORIG_REF_NAME = "axi_data_fifo_v2_1_28_axic_fifo" *) 
module design_1_auto_ds_0_axi_data_fifo_v2_1_28_axic_fifo
   (dout,
    full,
    empty,
    SR,
    din,
    access_is_incr_q_reg,
    access_is_fix_q_reg,
    \pushed_commands_reg[7] ,
    CLK,
    wr_en,
    \USE_WRITE.wr_cmd_b_ready ,
    out,
    incr_need_to_split_q,
    wrap_need_to_split_q,
    fix_need_to_split_q,
    access_is_incr_q,
    access_is_wrap_q,
    split_ongoing,
    Q,
    \gpr1.dout_i_reg[1] ,
    access_is_fix_q,
    \gpr1.dout_i_reg[1]_0 );
  output [4:0]dout;
  output full;
  output empty;
  output [0:0]SR;
  output [0:0]din;
  output access_is_incr_q_reg;
  output access_is_fix_q_reg;
  output \pushed_commands_reg[7] ;
  input CLK;
  input wr_en;
  input \USE_WRITE.wr_cmd_b_ready ;
  input out;
  input incr_need_to_split_q;
  input wrap_need_to_split_q;
  input fix_need_to_split_q;
  input access_is_incr_q;
  input access_is_wrap_q;
  input split_ongoing;
  input [7:0]Q;
  input [3:0]\gpr1.dout_i_reg[1] ;
  input access_is_fix_q;
  input [3:0]\gpr1.dout_i_reg[1]_0 ;

  wire CLK;
  wire [7:0]Q;
  wire [0:0]SR;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire access_is_fix_q;
  wire access_is_fix_q_reg;
  wire access_is_incr_q;
  wire access_is_incr_q_reg;
  wire access_is_wrap_q;
  wire [0:0]din;
  wire [4:0]dout;
  wire empty;
  wire fix_need_to_split_q;
  wire full;
  wire [3:0]\gpr1.dout_i_reg[1] ;
  wire [3:0]\gpr1.dout_i_reg[1]_0 ;
  wire incr_need_to_split_q;
  wire out;
  wire \pushed_commands_reg[7] ;
  wire split_ongoing;
  wire wr_en;
  wire wrap_need_to_split_q;

  design_1_auto_ds_0_axi_data_fifo_v2_1_28_fifo_gen inst
       (.CLK(CLK),
        .Q(Q),
        .SR(SR),
        .\USE_WRITE.wr_cmd_b_ready (\USE_WRITE.wr_cmd_b_ready ),
        .access_is_fix_q(access_is_fix_q),
        .access_is_fix_q_reg(access_is_fix_q_reg),
        .access_is_incr_q(access_is_incr_q),
        .access_is_incr_q_reg(access_is_incr_q_reg),
        .access_is_wrap_q(access_is_wrap_q),
        .din(din),
        .dout(dout),
        .empty(empty),
        .fix_need_to_split_q(fix_need_to_split_q),
        .full(full),
        .\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ),
        .\gpr1.dout_i_reg[1]_0 (\gpr1.dout_i_reg[1]_0 ),
        .incr_need_to_split_q(incr_need_to_split_q),
        .out(out),
        .\pushed_commands_reg[7] (\pushed_commands_reg[7] ),
        .split_ongoing(split_ongoing),
        .wr_en(wr_en),
        .wrap_need_to_split_q(wrap_need_to_split_q));
endmodule

(* ORIG_REF_NAME = "axi_data_fifo_v2_1_28_axic_fifo" *) 
module design_1_auto_ds_0_axi_data_fifo_v2_1_28_axic_fifo__parameterized0
   (dout,
    din,
    E,
    D,
    s_axi_arvalid_0,
    m_axi_arready_0,
    command_ongoing_reg,
    cmd_push_block_reg,
    cmd_push_block_reg_0,
    cmd_push_block_reg_1,
    m_axi_rvalid_0,
    m_axi_rvalid_1,
    m_axi_rvalid_2,
    m_axi_rvalid_3,
    s_axi_rdata,
    m_axi_arready_1,
    split_ongoing_reg,
    access_is_wrap_q_reg,
    s_axi_aresetn,
    s_axi_rvalid,
    m_axi_rvalid_4,
    m_axi_rready,
    \goreg_dm.dout_i_reg[17] ,
    \goreg_dm.dout_i_reg[2] ,
    s_axi_rlast,
    CLK,
    SR,
    access_fit_mi_side_q,
    \gpr1.dout_i_reg[15] ,
    Q,
    fix_need_to_split_q,
    \m_axi_arlen[7]_INST_0_i_1 ,
    access_is_wrap_q,
    split_ongoing,
    s_axi_arvalid,
    command_ongoing_reg_0,
    areset_d,
    command_ongoing,
    m_axi_arready,
    cmd_push_block,
    out,
    cmd_empty_reg,
    cmd_empty,
    m_axi_rvalid,
    s_axi_rvalid_0,
    s_axi_rready,
    \WORD_LANE[3].S_AXI_RDATA_II_reg[127] ,
    m_axi_rdata,
    p_3_in,
    m_axi_arvalid,
    s_axi_rid,
    access_is_fix_q,
    incr_need_to_split_q,
    wrap_need_to_split_q,
    \m_axi_arlen[7] ,
    \m_axi_arlen[7]_0 ,
    \m_axi_arlen[7]_INST_0_i_1_0 ,
    \m_axi_arlen[4] ,
    access_is_incr_q,
    \m_axi_arlen[7]_INST_0_i_10 ,
    \m_axi_arlen[7]_INST_0_i_10_0 ,
    \gpr1.dout_i_reg[15]_0 ,
    si_full_size_q,
    \gpr1.dout_i_reg[15]_1 ,
    \gpr1.dout_i_reg[15]_2 ,
    \gpr1.dout_i_reg[15]_3 ,
    \gpr1.dout_i_reg[15]_4 ,
    \m_axi_arlen[4]_INST_0_i_3 ,
    legal_wrap_len_q,
    \S_AXI_RRESP_ACC_reg[0] ,
    \current_word_1_reg[1] ,
    \S_AXI_RRESP_ACC_reg[0]_0 ,
    \current_word_1_reg[2] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1_reg[3] ,
    first_mi_word,
    \current_word_1_reg[3]_0 ,
    \s_axi_rdata[127]_INST_0_i_2 ,
    m_axi_rlast);
  output [19:0]dout;
  output [11:0]din;
  output [0:0]E;
  output [4:0]D;
  output s_axi_arvalid_0;
  output m_axi_arready_0;
  output command_ongoing_reg;
  output cmd_push_block_reg;
  output [0:0]cmd_push_block_reg_0;
  output cmd_push_block_reg_1;
  output [0:0]m_axi_rvalid_0;
  output [0:0]m_axi_rvalid_1;
  output [0:0]m_axi_rvalid_2;
  output [0:0]m_axi_rvalid_3;
  output [127:0]s_axi_rdata;
  output [0:0]m_axi_arready_1;
  output split_ongoing_reg;
  output access_is_wrap_q_reg;
  output [0:0]s_axi_aresetn;
  output s_axi_rvalid;
  output [0:0]m_axi_rvalid_4;
  output m_axi_rready;
  output [3:0]\goreg_dm.dout_i_reg[17] ;
  output \goreg_dm.dout_i_reg[2] ;
  output s_axi_rlast;
  input CLK;
  input [0:0]SR;
  input access_fit_mi_side_q;
  input [6:0]\gpr1.dout_i_reg[15] ;
  input [5:0]Q;
  input fix_need_to_split_q;
  input [7:0]\m_axi_arlen[7]_INST_0_i_1 ;
  input access_is_wrap_q;
  input split_ongoing;
  input s_axi_arvalid;
  input [0:0]command_ongoing_reg_0;
  input [1:0]areset_d;
  input command_ongoing;
  input m_axi_arready;
  input cmd_push_block;
  input out;
  input cmd_empty_reg;
  input cmd_empty;
  input m_axi_rvalid;
  input s_axi_rvalid_0;
  input s_axi_rready;
  input \WORD_LANE[3].S_AXI_RDATA_II_reg[127] ;
  input [31:0]m_axi_rdata;
  input [127:0]p_3_in;
  input [15:0]m_axi_arvalid;
  input [15:0]s_axi_rid;
  input access_is_fix_q;
  input incr_need_to_split_q;
  input wrap_need_to_split_q;
  input [7:0]\m_axi_arlen[7] ;
  input [7:0]\m_axi_arlen[7]_0 ;
  input [7:0]\m_axi_arlen[7]_INST_0_i_1_0 ;
  input [4:0]\m_axi_arlen[4] ;
  input access_is_incr_q;
  input [7:0]\m_axi_arlen[7]_INST_0_i_10 ;
  input [3:0]\m_axi_arlen[7]_INST_0_i_10_0 ;
  input \gpr1.dout_i_reg[15]_0 ;
  input si_full_size_q;
  input [1:0]\gpr1.dout_i_reg[15]_1 ;
  input [3:0]\gpr1.dout_i_reg[15]_2 ;
  input \gpr1.dout_i_reg[15]_3 ;
  input \gpr1.dout_i_reg[15]_4 ;
  input [4:0]\m_axi_arlen[4]_INST_0_i_3 ;
  input legal_wrap_len_q;
  input \S_AXI_RRESP_ACC_reg[0] ;
  input \current_word_1_reg[1] ;
  input \S_AXI_RRESP_ACC_reg[0]_0 ;
  input \current_word_1_reg[2] ;
  input \current_word_1_reg[1]_0 ;
  input [1:0]\current_word_1_reg[3] ;
  input first_mi_word;
  input \current_word_1_reg[3]_0 ;
  input \s_axi_rdata[127]_INST_0_i_2 ;
  input m_axi_rlast;

  wire CLK;
  wire [4:0]D;
  wire [0:0]E;
  wire [5:0]Q;
  wire [0:0]SR;
  wire \S_AXI_RRESP_ACC_reg[0] ;
  wire \S_AXI_RRESP_ACC_reg[0]_0 ;
  wire \WORD_LANE[3].S_AXI_RDATA_II_reg[127] ;
  wire access_fit_mi_side_q;
  wire access_is_fix_q;
  wire access_is_incr_q;
  wire access_is_wrap_q;
  wire access_is_wrap_q_reg;
  wire [1:0]areset_d;
  wire cmd_empty;
  wire cmd_empty_reg;
  wire cmd_push_block;
  wire cmd_push_block_reg;
  wire [0:0]cmd_push_block_reg_0;
  wire cmd_push_block_reg_1;
  wire command_ongoing;
  wire command_ongoing_reg;
  wire [0:0]command_ongoing_reg_0;
  wire \current_word_1_reg[1] ;
  wire \current_word_1_reg[1]_0 ;
  wire \current_word_1_reg[2] ;
  wire [1:0]\current_word_1_reg[3] ;
  wire \current_word_1_reg[3]_0 ;
  wire [11:0]din;
  wire [19:0]dout;
  wire first_mi_word;
  wire fix_need_to_split_q;
  wire [3:0]\goreg_dm.dout_i_reg[17] ;
  wire \goreg_dm.dout_i_reg[2] ;
  wire [6:0]\gpr1.dout_i_reg[15] ;
  wire \gpr1.dout_i_reg[15]_0 ;
  wire [1:0]\gpr1.dout_i_reg[15]_1 ;
  wire [3:0]\gpr1.dout_i_reg[15]_2 ;
  wire \gpr1.dout_i_reg[15]_3 ;
  wire \gpr1.dout_i_reg[15]_4 ;
  wire incr_need_to_split_q;
  wire legal_wrap_len_q;
  wire [4:0]\m_axi_arlen[4] ;
  wire [4:0]\m_axi_arlen[4]_INST_0_i_3 ;
  wire [7:0]\m_axi_arlen[7] ;
  wire [7:0]\m_axi_arlen[7]_0 ;
  wire [7:0]\m_axi_arlen[7]_INST_0_i_1 ;
  wire [7:0]\m_axi_arlen[7]_INST_0_i_10 ;
  wire [3:0]\m_axi_arlen[7]_INST_0_i_10_0 ;
  wire [7:0]\m_axi_arlen[7]_INST_0_i_1_0 ;
  wire m_axi_arready;
  wire m_axi_arready_0;
  wire [0:0]m_axi_arready_1;
  wire [15:0]m_axi_arvalid;
  wire [31:0]m_axi_rdata;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire m_axi_rvalid;
  wire [0:0]m_axi_rvalid_0;
  wire [0:0]m_axi_rvalid_1;
  wire [0:0]m_axi_rvalid_2;
  wire [0:0]m_axi_rvalid_3;
  wire [0:0]m_axi_rvalid_4;
  wire out;
  wire [127:0]p_3_in;
  wire [0:0]s_axi_aresetn;
  wire s_axi_arvalid;
  wire s_axi_arvalid_0;
  wire [127:0]s_axi_rdata;
  wire \s_axi_rdata[127]_INST_0_i_2 ;
  wire [15:0]s_axi_rid;
  wire s_axi_rlast;
  wire s_axi_rready;
  wire s_axi_rvalid;
  wire s_axi_rvalid_0;
  wire si_full_size_q;
  wire split_ongoing;
  wire split_ongoing_reg;
  wire wrap_need_to_split_q;

  design_1_auto_ds_0_axi_data_fifo_v2_1_28_fifo_gen__parameterized0 inst
       (.CLK(CLK),
        .D(D),
        .E(E),
        .Q(Q),
        .SR(SR),
        .\S_AXI_RRESP_ACC_reg[0] (\S_AXI_RRESP_ACC_reg[0] ),
        .\S_AXI_RRESP_ACC_reg[0]_0 (\S_AXI_RRESP_ACC_reg[0]_0 ),
        .\WORD_LANE[3].S_AXI_RDATA_II_reg[127] (\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .access_is_fix_q(access_is_fix_q),
        .access_is_incr_q(access_is_incr_q),
        .access_is_wrap_q(access_is_wrap_q),
        .access_is_wrap_q_reg(access_is_wrap_q_reg),
        .areset_d(areset_d),
        .cmd_empty(cmd_empty),
        .cmd_empty_reg(cmd_empty_reg),
        .cmd_push_block(cmd_push_block),
        .cmd_push_block_reg(cmd_push_block_reg),
        .cmd_push_block_reg_0(cmd_push_block_reg_0),
        .cmd_push_block_reg_1(cmd_push_block_reg_1),
        .command_ongoing(command_ongoing),
        .command_ongoing_reg(command_ongoing_reg),
        .command_ongoing_reg_0(command_ongoing_reg_0),
        .\current_word_1_reg[1] (\current_word_1_reg[1] ),
        .\current_word_1_reg[1]_0 (\current_word_1_reg[1]_0 ),
        .\current_word_1_reg[2] (\current_word_1_reg[2] ),
        .\current_word_1_reg[3] (\current_word_1_reg[3] ),
        .\current_word_1_reg[3]_0 (\current_word_1_reg[3]_0 ),
        .din(din),
        .dout(dout),
        .first_mi_word(first_mi_word),
        .fix_need_to_split_q(fix_need_to_split_q),
        .\goreg_dm.dout_i_reg[17] (\goreg_dm.dout_i_reg[17] ),
        .\goreg_dm.dout_i_reg[2] (\goreg_dm.dout_i_reg[2] ),
        .\gpr1.dout_i_reg[15] (\gpr1.dout_i_reg[15]_0 ),
        .\gpr1.dout_i_reg[15]_0 (\gpr1.dout_i_reg[15]_1 ),
        .\gpr1.dout_i_reg[15]_1 (\gpr1.dout_i_reg[15]_2 ),
        .\gpr1.dout_i_reg[15]_2 (\gpr1.dout_i_reg[15]_3 ),
        .\gpr1.dout_i_reg[15]_3 (\gpr1.dout_i_reg[15]_4 ),
        .incr_need_to_split_q(incr_need_to_split_q),
        .legal_wrap_len_q(legal_wrap_len_q),
        .\m_axi_arlen[4] (\m_axi_arlen[4] ),
        .\m_axi_arlen[4]_INST_0_i_3_0 (\m_axi_arlen[4]_INST_0_i_3 ),
        .\m_axi_arlen[7] (\m_axi_arlen[7] ),
        .\m_axi_arlen[7]_0 (\m_axi_arlen[7]_0 ),
        .\m_axi_arlen[7]_INST_0_i_10_0 (\m_axi_arlen[7]_INST_0_i_10 ),
        .\m_axi_arlen[7]_INST_0_i_10_1 (\m_axi_arlen[7]_INST_0_i_10_0 ),
        .\m_axi_arlen[7]_INST_0_i_1_0 (\m_axi_arlen[7]_INST_0_i_1 ),
        .\m_axi_arlen[7]_INST_0_i_1_1 (\m_axi_arlen[7]_INST_0_i_1_0 ),
        .m_axi_arready(m_axi_arready),
        .m_axi_arready_0(m_axi_arready_0),
        .m_axi_arready_1(m_axi_arready_1),
        .\m_axi_arsize[0] ({access_fit_mi_side_q,\gpr1.dout_i_reg[15] }),
        .m_axi_arvalid(m_axi_arvalid),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_rvalid_0(m_axi_rvalid_0),
        .m_axi_rvalid_1(m_axi_rvalid_1),
        .m_axi_rvalid_2(m_axi_rvalid_2),
        .m_axi_rvalid_3(m_axi_rvalid_3),
        .m_axi_rvalid_4(m_axi_rvalid_4),
        .out(out),
        .p_3_in(p_3_in),
        .s_axi_aresetn(s_axi_aresetn),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_arvalid_0(s_axi_arvalid_0),
        .s_axi_rdata(s_axi_rdata),
        .\s_axi_rdata[127]_INST_0_i_2_0 (\s_axi_rdata[127]_INST_0_i_2 ),
        .s_axi_rid(s_axi_rid),
        .s_axi_rlast(s_axi_rlast),
        .s_axi_rready(s_axi_rready),
        .s_axi_rvalid(s_axi_rvalid),
        .s_axi_rvalid_0(s_axi_rvalid_0),
        .si_full_size_q(si_full_size_q),
        .split_ongoing(split_ongoing),
        .split_ongoing_reg(split_ongoing_reg),
        .wrap_need_to_split_q(wrap_need_to_split_q));
endmodule

(* ORIG_REF_NAME = "axi_data_fifo_v2_1_28_axic_fifo" *) 
module design_1_auto_ds_0_axi_data_fifo_v2_1_28_axic_fifo__parameterized0__xdcDup__1
   (dout,
    access_fit_mi_side_q_reg,
    E,
    D,
    s_axi_awvalid_0,
    command_ongoing_reg,
    cmd_b_push_block_reg,
    cmd_b_push_block_reg_0,
    cmd_b_push_block_reg_1,
    cmd_push_block_reg,
    m_axi_awready_0,
    wr_en,
    split_ongoing_reg,
    access_is_wrap_q_reg,
    m_axi_wvalid,
    s_axi_wready,
    s_axi_wvalid_0,
    m_axi_wdata,
    m_axi_wstrb,
    \goreg_dm.dout_i_reg[17] ,
    \areset_d_reg[0] ,
    CLK,
    SR,
    din,
    Q,
    fix_need_to_split_q,
    \m_axi_awlen[7]_INST_0_i_6 ,
    access_is_wrap_q,
    split_ongoing,
    s_axi_awvalid,
    S_AXI_AREADY_I_reg,
    S_AXI_AREADY_I_reg_0,
    S_AXI_AREADY_I_reg_1,
    command_ongoing,
    m_axi_awready,
    command_ongoing_reg_0,
    cmd_b_push_block,
    out,
    \USE_WRITE.wr_cmd_b_ready ,
    \USE_B_CHANNEL.cmd_b_empty_i_reg ,
    cmd_b_empty,
    cmd_push_block,
    full,
    m_axi_awvalid_INST_0_i_1,
    s_axi_bid,
    access_is_fix_q,
    \m_axi_awlen[7] ,
    \m_axi_awlen[7]_0 ,
    \m_axi_awlen[7]_INST_0_i_6_0 ,
    wrap_need_to_split_q,
    \m_axi_awlen[4] ,
    incr_need_to_split_q,
    \m_axi_awlen[7]_INST_0_i_5 ,
    access_is_incr_q,
    \m_axi_awlen[7]_INST_0_i_5_0 ,
    \gpr1.dout_i_reg[15] ,
    si_full_size_q,
    \gpr1.dout_i_reg[15]_0 ,
    \gpr1.dout_i_reg[15]_1 ,
    \gpr1.dout_i_reg[15]_2 ,
    \gpr1.dout_i_reg[15]_3 ,
    \m_axi_awlen[4]_INST_0_i_3 ,
    legal_wrap_len_q,
    s_axi_wvalid,
    m_axi_wready,
    s_axi_wready_0,
    s_axi_wdata,
    s_axi_wstrb,
    \current_word_1_reg[3] ,
    first_mi_word,
    \current_word_1_reg[2] ,
    m_axi_wstrb_3_sp_1,
    \current_word_1_reg[1] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1_reg[3]_0 );
  output [15:0]dout;
  output [10:0]access_fit_mi_side_q_reg;
  output [0:0]E;
  output [4:0]D;
  output s_axi_awvalid_0;
  output command_ongoing_reg;
  output cmd_b_push_block_reg;
  output [0:0]cmd_b_push_block_reg_0;
  output cmd_b_push_block_reg_1;
  output cmd_push_block_reg;
  output [0:0]m_axi_awready_0;
  output wr_en;
  output split_ongoing_reg;
  output access_is_wrap_q_reg;
  output m_axi_wvalid;
  output s_axi_wready;
  output [0:0]s_axi_wvalid_0;
  output [31:0]m_axi_wdata;
  output [3:0]m_axi_wstrb;
  output [3:0]\goreg_dm.dout_i_reg[17] ;
  output \areset_d_reg[0] ;
  input CLK;
  input [0:0]SR;
  input [8:0]din;
  input [5:0]Q;
  input fix_need_to_split_q;
  input [7:0]\m_axi_awlen[7]_INST_0_i_6 ;
  input access_is_wrap_q;
  input split_ongoing;
  input s_axi_awvalid;
  input [0:0]S_AXI_AREADY_I_reg;
  input S_AXI_AREADY_I_reg_0;
  input S_AXI_AREADY_I_reg_1;
  input command_ongoing;
  input m_axi_awready;
  input command_ongoing_reg_0;
  input cmd_b_push_block;
  input out;
  input \USE_WRITE.wr_cmd_b_ready ;
  input \USE_B_CHANNEL.cmd_b_empty_i_reg ;
  input cmd_b_empty;
  input cmd_push_block;
  input full;
  input [15:0]m_axi_awvalid_INST_0_i_1;
  input [15:0]s_axi_bid;
  input access_is_fix_q;
  input [7:0]\m_axi_awlen[7] ;
  input [7:0]\m_axi_awlen[7]_0 ;
  input [7:0]\m_axi_awlen[7]_INST_0_i_6_0 ;
  input wrap_need_to_split_q;
  input [4:0]\m_axi_awlen[4] ;
  input incr_need_to_split_q;
  input \m_axi_awlen[7]_INST_0_i_5 ;
  input access_is_incr_q;
  input \m_axi_awlen[7]_INST_0_i_5_0 ;
  input \gpr1.dout_i_reg[15] ;
  input si_full_size_q;
  input [1:0]\gpr1.dout_i_reg[15]_0 ;
  input [3:0]\gpr1.dout_i_reg[15]_1 ;
  input \gpr1.dout_i_reg[15]_2 ;
  input \gpr1.dout_i_reg[15]_3 ;
  input [4:0]\m_axi_awlen[4]_INST_0_i_3 ;
  input legal_wrap_len_q;
  input s_axi_wvalid;
  input m_axi_wready;
  input s_axi_wready_0;
  input [127:0]s_axi_wdata;
  input [15:0]s_axi_wstrb;
  input [2:0]\current_word_1_reg[3] ;
  input first_mi_word;
  input \current_word_1_reg[2] ;
  input m_axi_wstrb_3_sp_1;
  input \current_word_1_reg[1] ;
  input \current_word_1_reg[1]_0 ;
  input \current_word_1_reg[3]_0 ;

  wire CLK;
  wire [4:0]D;
  wire [0:0]E;
  wire [5:0]Q;
  wire [0:0]SR;
  wire [0:0]S_AXI_AREADY_I_reg;
  wire S_AXI_AREADY_I_reg_0;
  wire S_AXI_AREADY_I_reg_1;
  wire \USE_B_CHANNEL.cmd_b_empty_i_reg ;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire [10:0]access_fit_mi_side_q_reg;
  wire access_is_fix_q;
  wire access_is_incr_q;
  wire access_is_wrap_q;
  wire access_is_wrap_q_reg;
  wire \areset_d_reg[0] ;
  wire cmd_b_empty;
  wire cmd_b_push_block;
  wire cmd_b_push_block_reg;
  wire [0:0]cmd_b_push_block_reg_0;
  wire cmd_b_push_block_reg_1;
  wire cmd_push_block;
  wire cmd_push_block_reg;
  wire command_ongoing;
  wire command_ongoing_reg;
  wire command_ongoing_reg_0;
  wire \current_word_1_reg[1] ;
  wire \current_word_1_reg[1]_0 ;
  wire \current_word_1_reg[2] ;
  wire [2:0]\current_word_1_reg[3] ;
  wire \current_word_1_reg[3]_0 ;
  wire [8:0]din;
  wire [15:0]dout;
  wire first_mi_word;
  wire fix_need_to_split_q;
  wire full;
  wire [3:0]\goreg_dm.dout_i_reg[17] ;
  wire \gpr1.dout_i_reg[15] ;
  wire [1:0]\gpr1.dout_i_reg[15]_0 ;
  wire [3:0]\gpr1.dout_i_reg[15]_1 ;
  wire \gpr1.dout_i_reg[15]_2 ;
  wire \gpr1.dout_i_reg[15]_3 ;
  wire incr_need_to_split_q;
  wire legal_wrap_len_q;
  wire [4:0]\m_axi_awlen[4] ;
  wire [4:0]\m_axi_awlen[4]_INST_0_i_3 ;
  wire [7:0]\m_axi_awlen[7] ;
  wire [7:0]\m_axi_awlen[7]_0 ;
  wire \m_axi_awlen[7]_INST_0_i_5 ;
  wire \m_axi_awlen[7]_INST_0_i_5_0 ;
  wire [7:0]\m_axi_awlen[7]_INST_0_i_6 ;
  wire [7:0]\m_axi_awlen[7]_INST_0_i_6_0 ;
  wire m_axi_awready;
  wire [0:0]m_axi_awready_0;
  wire [15:0]m_axi_awvalid_INST_0_i_1;
  wire [31:0]m_axi_wdata;
  wire m_axi_wready;
  wire [3:0]m_axi_wstrb;
  wire m_axi_wstrb_3_sn_1;
  wire m_axi_wvalid;
  wire out;
  wire s_axi_awvalid;
  wire s_axi_awvalid_0;
  wire [15:0]s_axi_bid;
  wire [127:0]s_axi_wdata;
  wire s_axi_wready;
  wire s_axi_wready_0;
  wire [15:0]s_axi_wstrb;
  wire s_axi_wvalid;
  wire [0:0]s_axi_wvalid_0;
  wire si_full_size_q;
  wire split_ongoing;
  wire split_ongoing_reg;
  wire wr_en;
  wire wrap_need_to_split_q;

  assign m_axi_wstrb_3_sn_1 = m_axi_wstrb_3_sp_1;
  design_1_auto_ds_0_axi_data_fifo_v2_1_28_fifo_gen__parameterized0__xdcDup__1 inst
       (.CLK(CLK),
        .D(D),
        .E(E),
        .Q(Q),
        .SR(SR),
        .S_AXI_AREADY_I_reg(S_AXI_AREADY_I_reg),
        .S_AXI_AREADY_I_reg_0(S_AXI_AREADY_I_reg_0),
        .S_AXI_AREADY_I_reg_1(S_AXI_AREADY_I_reg_1),
        .\USE_B_CHANNEL.cmd_b_empty_i_reg (\USE_B_CHANNEL.cmd_b_empty_i_reg ),
        .\USE_WRITE.wr_cmd_b_ready (\USE_WRITE.wr_cmd_b_ready ),
        .access_fit_mi_side_q_reg(access_fit_mi_side_q_reg),
        .access_is_fix_q(access_is_fix_q),
        .access_is_incr_q(access_is_incr_q),
        .access_is_wrap_q(access_is_wrap_q),
        .access_is_wrap_q_reg(access_is_wrap_q_reg),
        .\areset_d_reg[0] (\areset_d_reg[0] ),
        .cmd_b_empty(cmd_b_empty),
        .cmd_b_push_block(cmd_b_push_block),
        .cmd_b_push_block_reg(cmd_b_push_block_reg),
        .cmd_b_push_block_reg_0(cmd_b_push_block_reg_0),
        .cmd_b_push_block_reg_1(cmd_b_push_block_reg_1),
        .cmd_push_block(cmd_push_block),
        .cmd_push_block_reg(cmd_push_block_reg),
        .command_ongoing(command_ongoing),
        .command_ongoing_reg(command_ongoing_reg),
        .command_ongoing_reg_0(command_ongoing_reg_0),
        .\current_word_1_reg[1] (\current_word_1_reg[1] ),
        .\current_word_1_reg[1]_0 (\current_word_1_reg[1]_0 ),
        .\current_word_1_reg[2] (\current_word_1_reg[2] ),
        .\current_word_1_reg[3] (\current_word_1_reg[3] ),
        .\current_word_1_reg[3]_0 (\current_word_1_reg[3]_0 ),
        .din(din),
        .dout(dout),
        .first_mi_word(first_mi_word),
        .fix_need_to_split_q(fix_need_to_split_q),
        .full(full),
        .\goreg_dm.dout_i_reg[17] (\goreg_dm.dout_i_reg[17] ),
        .\gpr1.dout_i_reg[15] (\gpr1.dout_i_reg[15] ),
        .\gpr1.dout_i_reg[15]_0 (\gpr1.dout_i_reg[15]_0 ),
        .\gpr1.dout_i_reg[15]_1 (\gpr1.dout_i_reg[15]_1 ),
        .\gpr1.dout_i_reg[15]_2 (\gpr1.dout_i_reg[15]_2 ),
        .\gpr1.dout_i_reg[15]_3 (\gpr1.dout_i_reg[15]_3 ),
        .incr_need_to_split_q(incr_need_to_split_q),
        .legal_wrap_len_q(legal_wrap_len_q),
        .\m_axi_awlen[4] (\m_axi_awlen[4] ),
        .\m_axi_awlen[4]_INST_0_i_3_0 (\m_axi_awlen[4]_INST_0_i_3 ),
        .\m_axi_awlen[7] (\m_axi_awlen[7] ),
        .\m_axi_awlen[7]_0 (\m_axi_awlen[7]_0 ),
        .\m_axi_awlen[7]_INST_0_i_5_0 (\m_axi_awlen[7]_INST_0_i_5 ),
        .\m_axi_awlen[7]_INST_0_i_5_1 (\m_axi_awlen[7]_INST_0_i_5_0 ),
        .\m_axi_awlen[7]_INST_0_i_6_0 (\m_axi_awlen[7]_INST_0_i_6 ),
        .\m_axi_awlen[7]_INST_0_i_6_1 (\m_axi_awlen[7]_INST_0_i_6_0 ),
        .m_axi_awready(m_axi_awready),
        .m_axi_awready_0(m_axi_awready_0),
        .m_axi_awvalid_INST_0_i_1_0(m_axi_awvalid_INST_0_i_1),
        .m_axi_wdata(m_axi_wdata),
        .m_axi_wready(m_axi_wready),
        .m_axi_wstrb(m_axi_wstrb),
        .m_axi_wstrb_3_sp_1(m_axi_wstrb_3_sn_1),
        .m_axi_wvalid(m_axi_wvalid),
        .out(out),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_awvalid_0(s_axi_awvalid_0),
        .s_axi_bid(s_axi_bid),
        .s_axi_wdata(s_axi_wdata),
        .s_axi_wready(s_axi_wready),
        .s_axi_wready_0(s_axi_wready_0),
        .s_axi_wstrb(s_axi_wstrb),
        .s_axi_wvalid(s_axi_wvalid),
        .s_axi_wvalid_0(s_axi_wvalid_0),
        .si_full_size_q(si_full_size_q),
        .split_ongoing(split_ongoing),
        .split_ongoing_reg(split_ongoing_reg),
        .wr_en(wr_en),
        .wrap_need_to_split_q(wrap_need_to_split_q));
endmodule

(* ORIG_REF_NAME = "axi_data_fifo_v2_1_28_fifo_gen" *) 
module design_1_auto_ds_0_axi_data_fifo_v2_1_28_fifo_gen
   (dout,
    full,
    empty,
    SR,
    din,
    access_is_incr_q_reg,
    access_is_fix_q_reg,
    \pushed_commands_reg[7] ,
    CLK,
    wr_en,
    \USE_WRITE.wr_cmd_b_ready ,
    out,
    incr_need_to_split_q,
    wrap_need_to_split_q,
    fix_need_to_split_q,
    access_is_incr_q,
    access_is_wrap_q,
    split_ongoing,
    Q,
    \gpr1.dout_i_reg[1] ,
    access_is_fix_q,
    \gpr1.dout_i_reg[1]_0 );
  output [4:0]dout;
  output full;
  output empty;
  output [0:0]SR;
  output [0:0]din;
  output access_is_incr_q_reg;
  output access_is_fix_q_reg;
  output \pushed_commands_reg[7] ;
  input CLK;
  input wr_en;
  input \USE_WRITE.wr_cmd_b_ready ;
  input out;
  input incr_need_to_split_q;
  input wrap_need_to_split_q;
  input fix_need_to_split_q;
  input access_is_incr_q;
  input access_is_wrap_q;
  input split_ongoing;
  input [7:0]Q;
  input [3:0]\gpr1.dout_i_reg[1] ;
  input access_is_fix_q;
  input [3:0]\gpr1.dout_i_reg[1]_0 ;

  wire CLK;
  wire [7:0]Q;
  wire [0:0]SR;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire access_is_fix_q;
  wire access_is_fix_q_reg;
  wire access_is_incr_q;
  wire access_is_incr_q_reg;
  wire access_is_wrap_q;
  wire [0:0]din;
  wire [4:0]dout;
  wire empty;
  wire fix_need_to_split_q;
  wire full;
  wire [3:0]\gpr1.dout_i_reg[1] ;
  wire [3:0]\gpr1.dout_i_reg[1]_0 ;
  wire incr_need_to_split_q;
  wire \m_axi_awlen[7]_INST_0_i_17_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_18_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_19_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_20_n_0 ;
  wire out;
  wire [3:0]p_1_out;
  wire \pushed_commands_reg[7] ;
  wire split_ongoing;
  wire wr_en;
  wire wrap_need_to_split_q;
  wire NLW_fifo_gen_inst_almost_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_almost_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED;
  wire NLW_fifo_gen_inst_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_valid_UNCONNECTED;
  wire NLW_fifo_gen_inst_wr_ack_UNCONNECTED;
  wire NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_data_count_UNCONNECTED;
  wire [7:4]NLW_fifo_gen_inst_dout_UNCONNECTED;
  wire [31:0]NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED;
  wire [31:0]NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_rd_data_count_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_wr_data_count_UNCONNECTED;

  LUT1 #(
    .INIT(2'h1)) 
    S_AXI_AREADY_I_i_1
       (.I0(out),
        .O(SR));
  (* C_ADD_NGC_CONSTRAINT = "0" *) 
  (* C_APPLICATION_TYPE_AXIS = "0" *) 
  (* C_APPLICATION_TYPE_RACH = "0" *) 
  (* C_APPLICATION_TYPE_RDCH = "0" *) 
  (* C_APPLICATION_TYPE_WACH = "0" *) 
  (* C_APPLICATION_TYPE_WDCH = "0" *) 
  (* C_APPLICATION_TYPE_WRCH = "0" *) 
  (* C_AXIS_TDATA_WIDTH = "64" *) 
  (* C_AXIS_TDEST_WIDTH = "4" *) 
  (* C_AXIS_TID_WIDTH = "8" *) 
  (* C_AXIS_TKEEP_WIDTH = "4" *) 
  (* C_AXIS_TSTRB_WIDTH = "4" *) 
  (* C_AXIS_TUSER_WIDTH = "4" *) 
  (* C_AXIS_TYPE = "0" *) 
  (* C_AXI_ADDR_WIDTH = "32" *) 
  (* C_AXI_ARUSER_WIDTH = "1" *) 
  (* C_AXI_AWUSER_WIDTH = "1" *) 
  (* C_AXI_BUSER_WIDTH = "1" *) 
  (* C_AXI_DATA_WIDTH = "64" *) 
  (* C_AXI_ID_WIDTH = "4" *) 
  (* C_AXI_LEN_WIDTH = "8" *) 
  (* C_AXI_LOCK_WIDTH = "2" *) 
  (* C_AXI_RUSER_WIDTH = "1" *) 
  (* C_AXI_TYPE = "0" *) 
  (* C_AXI_WUSER_WIDTH = "1" *) 
  (* C_COMMON_CLOCK = "1" *) 
  (* C_COUNT_TYPE = "0" *) 
  (* C_DATA_COUNT_WIDTH = "6" *) 
  (* C_DEFAULT_VALUE = "BlankString" *) 
  (* C_DIN_WIDTH = "9" *) 
  (* C_DIN_WIDTH_AXIS = "1" *) 
  (* C_DIN_WIDTH_RACH = "32" *) 
  (* C_DIN_WIDTH_RDCH = "64" *) 
  (* C_DIN_WIDTH_WACH = "32" *) 
  (* C_DIN_WIDTH_WDCH = "64" *) 
  (* C_DIN_WIDTH_WRCH = "2" *) 
  (* C_DOUT_RST_VAL = "0" *) 
  (* C_DOUT_WIDTH = "9" *) 
  (* C_ENABLE_RLOCS = "0" *) 
  (* C_ENABLE_RST_SYNC = "1" *) 
  (* C_EN_SAFETY_CKT = "0" *) 
  (* C_ERROR_INJECTION_TYPE = "0" *) 
  (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) 
  (* C_FAMILY = "zynquplus" *) 
  (* C_FULL_FLAGS_RST_VAL = "0" *) 
  (* C_HAS_ALMOST_EMPTY = "0" *) 
  (* C_HAS_ALMOST_FULL = "0" *) 
  (* C_HAS_AXIS_TDATA = "0" *) 
  (* C_HAS_AXIS_TDEST = "0" *) 
  (* C_HAS_AXIS_TID = "0" *) 
  (* C_HAS_AXIS_TKEEP = "0" *) 
  (* C_HAS_AXIS_TLAST = "0" *) 
  (* C_HAS_AXIS_TREADY = "1" *) 
  (* C_HAS_AXIS_TSTRB = "0" *) 
  (* C_HAS_AXIS_TUSER = "0" *) 
  (* C_HAS_AXI_ARUSER = "0" *) 
  (* C_HAS_AXI_AWUSER = "0" *) 
  (* C_HAS_AXI_BUSER = "0" *) 
  (* C_HAS_AXI_ID = "0" *) 
  (* C_HAS_AXI_RD_CHANNEL = "0" *) 
  (* C_HAS_AXI_RUSER = "0" *) 
  (* C_HAS_AXI_WR_CHANNEL = "0" *) 
  (* C_HAS_AXI_WUSER = "0" *) 
  (* C_HAS_BACKUP = "0" *) 
  (* C_HAS_DATA_COUNT = "0" *) 
  (* C_HAS_DATA_COUNTS_AXIS = "0" *) 
  (* C_HAS_DATA_COUNTS_RACH = "0" *) 
  (* C_HAS_DATA_COUNTS_RDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WACH = "0" *) 
  (* C_HAS_DATA_COUNTS_WDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WRCH = "0" *) 
  (* C_HAS_INT_CLK = "0" *) 
  (* C_HAS_MASTER_CE = "0" *) 
  (* C_HAS_MEMINIT_FILE = "0" *) 
  (* C_HAS_OVERFLOW = "0" *) 
  (* C_HAS_PROG_FLAGS_AXIS = "0" *) 
  (* C_HAS_PROG_FLAGS_RACH = "0" *) 
  (* C_HAS_PROG_FLAGS_RDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WACH = "0" *) 
  (* C_HAS_PROG_FLAGS_WDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WRCH = "0" *) 
  (* C_HAS_RD_DATA_COUNT = "0" *) 
  (* C_HAS_RD_RST = "0" *) 
  (* C_HAS_RST = "1" *) 
  (* C_HAS_SLAVE_CE = "0" *) 
  (* C_HAS_SRST = "0" *) 
  (* C_HAS_UNDERFLOW = "0" *) 
  (* C_HAS_VALID = "0" *) 
  (* C_HAS_WR_ACK = "0" *) 
  (* C_HAS_WR_DATA_COUNT = "0" *) 
  (* C_HAS_WR_RST = "0" *) 
  (* C_IMPLEMENTATION_TYPE = "0" *) 
  (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RACH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WACH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) 
  (* C_INIT_WR_PNTR_VAL = "0" *) 
  (* C_INTERFACE_TYPE = "0" *) 
  (* C_MEMORY_TYPE = "2" *) 
  (* C_MIF_FILE_NAME = "BlankString" *) 
  (* C_MSGON_VAL = "1" *) 
  (* C_OPTIMIZATION_MODE = "0" *) 
  (* C_OVERFLOW_LOW = "0" *) 
  (* C_POWER_SAVING_MODE = "0" *) 
  (* C_PRELOAD_LATENCY = "0" *) 
  (* C_PRELOAD_REGS = "1" *) 
  (* C_PRIM_FIFO_TYPE = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) 
  (* C_PROG_EMPTY_TYPE = "0" *) 
  (* C_PROG_EMPTY_TYPE_AXIS = "0" *) 
  (* C_PROG_EMPTY_TYPE_RACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_RDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WRCH = "0" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL = "31" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) 
  (* C_PROG_FULL_THRESH_NEGATE_VAL = "30" *) 
  (* C_PROG_FULL_TYPE = "0" *) 
  (* C_PROG_FULL_TYPE_AXIS = "0" *) 
  (* C_PROG_FULL_TYPE_RACH = "0" *) 
  (* C_PROG_FULL_TYPE_RDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WACH = "0" *) 
  (* C_PROG_FULL_TYPE_WDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WRCH = "0" *) 
  (* C_RACH_TYPE = "0" *) 
  (* C_RDCH_TYPE = "0" *) 
  (* C_RD_DATA_COUNT_WIDTH = "6" *) 
  (* C_RD_DEPTH = "32" *) 
  (* C_RD_FREQ = "1" *) 
  (* C_RD_PNTR_WIDTH = "5" *) 
  (* C_REG_SLICE_MODE_AXIS = "0" *) 
  (* C_REG_SLICE_MODE_RACH = "0" *) 
  (* C_REG_SLICE_MODE_RDCH = "0" *) 
  (* C_REG_SLICE_MODE_WACH = "0" *) 
  (* C_REG_SLICE_MODE_WDCH = "0" *) 
  (* C_REG_SLICE_MODE_WRCH = "0" *) 
  (* C_SELECT_XPM = "0" *) 
  (* C_SYNCHRONIZER_STAGE = "3" *) 
  (* C_UNDERFLOW_LOW = "0" *) 
  (* C_USE_COMMON_OVERFLOW = "0" *) 
  (* C_USE_COMMON_UNDERFLOW = "0" *) 
  (* C_USE_DEFAULT_SETTINGS = "0" *) 
  (* C_USE_DOUT_RST = "0" *) 
  (* C_USE_ECC = "0" *) 
  (* C_USE_ECC_AXIS = "0" *) 
  (* C_USE_ECC_RACH = "0" *) 
  (* C_USE_ECC_RDCH = "0" *) 
  (* C_USE_ECC_WACH = "0" *) 
  (* C_USE_ECC_WDCH = "0" *) 
  (* C_USE_ECC_WRCH = "0" *) 
  (* C_USE_EMBEDDED_REG = "0" *) 
  (* C_USE_FIFO16_FLAGS = "0" *) 
  (* C_USE_FWFT_DATA_COUNT = "1" *) 
  (* C_USE_PIPELINE_REG = "0" *) 
  (* C_VALID_LOW = "0" *) 
  (* C_WACH_TYPE = "0" *) 
  (* C_WDCH_TYPE = "0" *) 
  (* C_WRCH_TYPE = "0" *) 
  (* C_WR_ACK_LOW = "0" *) 
  (* C_WR_DATA_COUNT_WIDTH = "6" *) 
  (* C_WR_DEPTH = "32" *) 
  (* C_WR_DEPTH_AXIS = "1024" *) 
  (* C_WR_DEPTH_RACH = "16" *) 
  (* C_WR_DEPTH_RDCH = "1024" *) 
  (* C_WR_DEPTH_WACH = "16" *) 
  (* C_WR_DEPTH_WDCH = "1024" *) 
  (* C_WR_DEPTH_WRCH = "16" *) 
  (* C_WR_FREQ = "1" *) 
  (* C_WR_PNTR_WIDTH = "5" *) 
  (* C_WR_PNTR_WIDTH_AXIS = "10" *) 
  (* C_WR_PNTR_WIDTH_RACH = "4" *) 
  (* C_WR_PNTR_WIDTH_RDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WACH = "4" *) 
  (* C_WR_PNTR_WIDTH_WDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WRCH = "4" *) 
  (* C_WR_RESPONSE_LATENCY = "1" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* is_du_within_envelope = "true" *) 
  design_1_auto_ds_0_fifo_generator_v13_2_9 fifo_gen_inst
       (.almost_empty(NLW_fifo_gen_inst_almost_empty_UNCONNECTED),
        .almost_full(NLW_fifo_gen_inst_almost_full_UNCONNECTED),
        .axi_ar_data_count(NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED[4:0]),
        .axi_ar_dbiterr(NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED),
        .axi_ar_injectdbiterr(1'b0),
        .axi_ar_injectsbiterr(1'b0),
        .axi_ar_overflow(NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED),
        .axi_ar_prog_empty(NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED),
        .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_prog_full(NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED),
        .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_rd_data_count(NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED[4:0]),
        .axi_ar_sbiterr(NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED),
        .axi_ar_underflow(NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED),
        .axi_ar_wr_data_count(NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED[4:0]),
        .axi_aw_data_count(NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED[4:0]),
        .axi_aw_dbiterr(NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED),
        .axi_aw_injectdbiterr(1'b0),
        .axi_aw_injectsbiterr(1'b0),
        .axi_aw_overflow(NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED),
        .axi_aw_prog_empty(NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED),
        .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_prog_full(NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED),
        .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_rd_data_count(NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED[4:0]),
        .axi_aw_sbiterr(NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED),
        .axi_aw_underflow(NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED),
        .axi_aw_wr_data_count(NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED[4:0]),
        .axi_b_data_count(NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED[4:0]),
        .axi_b_dbiterr(NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED),
        .axi_b_injectdbiterr(1'b0),
        .axi_b_injectsbiterr(1'b0),
        .axi_b_overflow(NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED),
        .axi_b_prog_empty(NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED),
        .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_prog_full(NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED),
        .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_rd_data_count(NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED[4:0]),
        .axi_b_sbiterr(NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED),
        .axi_b_underflow(NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED),
        .axi_b_wr_data_count(NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED[4:0]),
        .axi_r_data_count(NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED[10:0]),
        .axi_r_dbiterr(NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED),
        .axi_r_injectdbiterr(1'b0),
        .axi_r_injectsbiterr(1'b0),
        .axi_r_overflow(NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED),
        .axi_r_prog_empty(NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED),
        .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_prog_full(NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED),
        .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_rd_data_count(NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED[10:0]),
        .axi_r_sbiterr(NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED),
        .axi_r_underflow(NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED),
        .axi_r_wr_data_count(NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED[10:0]),
        .axi_w_data_count(NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED[10:0]),
        .axi_w_dbiterr(NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED),
        .axi_w_injectdbiterr(1'b0),
        .axi_w_injectsbiterr(1'b0),
        .axi_w_overflow(NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED),
        .axi_w_prog_empty(NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED),
        .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_prog_full(NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED),
        .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_rd_data_count(NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED[10:0]),
        .axi_w_sbiterr(NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED),
        .axi_w_underflow(NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED),
        .axi_w_wr_data_count(NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED[10:0]),
        .axis_data_count(NLW_fifo_gen_inst_axis_data_count_UNCONNECTED[10:0]),
        .axis_dbiterr(NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED),
        .axis_injectdbiterr(1'b0),
        .axis_injectsbiterr(1'b0),
        .axis_overflow(NLW_fifo_gen_inst_axis_overflow_UNCONNECTED),
        .axis_prog_empty(NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED),
        .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_prog_full(NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED),
        .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_rd_data_count(NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED[10:0]),
        .axis_sbiterr(NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED),
        .axis_underflow(NLW_fifo_gen_inst_axis_underflow_UNCONNECTED),
        .axis_wr_data_count(NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED[10:0]),
        .backup(1'b0),
        .backup_marker(1'b0),
        .clk(CLK),
        .data_count(NLW_fifo_gen_inst_data_count_UNCONNECTED[5:0]),
        .dbiterr(NLW_fifo_gen_inst_dbiterr_UNCONNECTED),
        .din({din,1'b0,1'b0,1'b0,1'b0,p_1_out}),
        .dout({dout[4],NLW_fifo_gen_inst_dout_UNCONNECTED[7:4],dout[3:0]}),
        .empty(empty),
        .full(full),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .int_clk(1'b0),
        .m_aclk(1'b0),
        .m_aclk_en(1'b0),
        .m_axi_araddr(NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED[31:0]),
        .m_axi_arburst(NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED[1:0]),
        .m_axi_arcache(NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED[3:0]),
        .m_axi_arid(NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED[3:0]),
        .m_axi_arlen(NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED[7:0]),
        .m_axi_arlock(NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED[1:0]),
        .m_axi_arprot(NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED[2:0]),
        .m_axi_arqos(NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED[3:0]),
        .m_axi_arready(1'b0),
        .m_axi_arregion(NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED[3:0]),
        .m_axi_arsize(NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED[2:0]),
        .m_axi_aruser(NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED[0]),
        .m_axi_arvalid(NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED),
        .m_axi_awaddr(NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED[31:0]),
        .m_axi_awburst(NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED[1:0]),
        .m_axi_awcache(NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED[3:0]),
        .m_axi_awid(NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED[3:0]),
        .m_axi_awlen(NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED[7:0]),
        .m_axi_awlock(NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED[1:0]),
        .m_axi_awprot(NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED[2:0]),
        .m_axi_awqos(NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED[3:0]),
        .m_axi_awready(1'b0),
        .m_axi_awregion(NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED[3:0]),
        .m_axi_awsize(NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED[2:0]),
        .m_axi_awuser(NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED[0]),
        .m_axi_awvalid(NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED),
        .m_axi_bid({1'b0,1'b0,1'b0,1'b0}),
        .m_axi_bready(NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED),
        .m_axi_bresp({1'b0,1'b0}),
        .m_axi_buser(1'b0),
        .m_axi_bvalid(1'b0),
        .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rid({1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rlast(1'b0),
        .m_axi_rready(NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED),
        .m_axi_rresp({1'b0,1'b0}),
        .m_axi_ruser(1'b0),
        .m_axi_rvalid(1'b0),
        .m_axi_wdata(NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED[63:0]),
        .m_axi_wid(NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED[3:0]),
        .m_axi_wlast(NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED),
        .m_axi_wready(1'b0),
        .m_axi_wstrb(NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED[7:0]),
        .m_axi_wuser(NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED[0]),
        .m_axi_wvalid(NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED),
        .m_axis_tdata(NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED[63:0]),
        .m_axis_tdest(NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED[3:0]),
        .m_axis_tid(NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED[7:0]),
        .m_axis_tkeep(NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED[3:0]),
        .m_axis_tlast(NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED),
        .m_axis_tready(1'b0),
        .m_axis_tstrb(NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED[3:0]),
        .m_axis_tuser(NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED[3:0]),
        .m_axis_tvalid(NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED),
        .overflow(NLW_fifo_gen_inst_overflow_UNCONNECTED),
        .prog_empty(NLW_fifo_gen_inst_prog_empty_UNCONNECTED),
        .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full(NLW_fifo_gen_inst_prog_full_UNCONNECTED),
        .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rd_clk(1'b0),
        .rd_data_count(NLW_fifo_gen_inst_rd_data_count_UNCONNECTED[5:0]),
        .rd_en(\USE_WRITE.wr_cmd_b_ready ),
        .rd_rst(1'b0),
        .rd_rst_busy(NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED),
        .rst(SR),
        .s_aclk(1'b0),
        .s_aclk_en(1'b0),
        .s_aresetn(1'b0),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlock({1'b0,1'b0}),
        .s_axi_arprot({1'b0,1'b0,1'b0}),
        .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED),
        .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_aruser(1'b0),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlock({1'b0,1'b0}),
        .s_axi_awprot({1'b0,1'b0,1'b0}),
        .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED),
        .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awuser(1'b0),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED[3:0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_buser(NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED[0]),
        .s_axi_bvalid(NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED),
        .s_axi_rdata(NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED[63:0]),
        .s_axi_rid(NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED[3:0]),
        .s_axi_rlast(NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_ruser(NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED[0]),
        .s_axi_rvalid(NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wuser(1'b0),
        .s_axi_wvalid(1'b0),
        .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tdest({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tkeep({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tlast(1'b0),
        .s_axis_tready(NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED),
        .s_axis_tstrb({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tvalid(1'b0),
        .sbiterr(NLW_fifo_gen_inst_sbiterr_UNCONNECTED),
        .sleep(1'b0),
        .srst(1'b0),
        .underflow(NLW_fifo_gen_inst_underflow_UNCONNECTED),
        .valid(NLW_fifo_gen_inst_valid_UNCONNECTED),
        .wr_ack(NLW_fifo_gen_inst_wr_ack_UNCONNECTED),
        .wr_clk(1'b0),
        .wr_data_count(NLW_fifo_gen_inst_wr_data_count_UNCONNECTED[5:0]),
        .wr_en(wr_en),
        .wr_rst(1'b0),
        .wr_rst_busy(NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED));
  LUT4 #(
    .INIT(16'hAAA8)) 
    fifo_gen_inst_i_1__0
       (.I0(access_is_incr_q_reg),
        .I1(incr_need_to_split_q),
        .I2(wrap_need_to_split_q),
        .I3(fix_need_to_split_q),
        .O(din));
  LUT4 #(
    .INIT(16'hB888)) 
    fifo_gen_inst_i_2__1
       (.I0(\gpr1.dout_i_reg[1]_0 [3]),
        .I1(fix_need_to_split_q),
        .I2(incr_need_to_split_q),
        .I3(\gpr1.dout_i_reg[1] [3]),
        .O(p_1_out[3]));
  LUT4 #(
    .INIT(16'hB888)) 
    fifo_gen_inst_i_3__1
       (.I0(\gpr1.dout_i_reg[1]_0 [2]),
        .I1(fix_need_to_split_q),
        .I2(incr_need_to_split_q),
        .I3(\gpr1.dout_i_reg[1] [2]),
        .O(p_1_out[2]));
  LUT4 #(
    .INIT(16'hB888)) 
    fifo_gen_inst_i_4__1
       (.I0(\gpr1.dout_i_reg[1]_0 [1]),
        .I1(fix_need_to_split_q),
        .I2(incr_need_to_split_q),
        .I3(\gpr1.dout_i_reg[1] [1]),
        .O(p_1_out[1]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    fifo_gen_inst_i_5__1
       (.I0(\gpr1.dout_i_reg[1]_0 [0]),
        .I1(fix_need_to_split_q),
        .I2(\gpr1.dout_i_reg[1] [0]),
        .I3(incr_need_to_split_q),
        .I4(wrap_need_to_split_q),
        .O(p_1_out[0]));
  LUT6 #(
    .INIT(64'h00A2A2A200A200A2)) 
    fifo_gen_inst_i_8
       (.I0(access_is_fix_q_reg),
        .I1(access_is_incr_q),
        .I2(\pushed_commands_reg[7] ),
        .I3(access_is_wrap_q),
        .I4(split_ongoing),
        .I5(wrap_need_to_split_q),
        .O(access_is_incr_q_reg));
  LUT6 #(
    .INIT(64'hDDDDDDDDDDDDDDD5)) 
    \m_axi_awlen[7]_INST_0_i_14 
       (.I0(access_is_fix_q),
        .I1(fix_need_to_split_q),
        .I2(\m_axi_awlen[7]_INST_0_i_17_n_0 ),
        .I3(\m_axi_awlen[7]_INST_0_i_18_n_0 ),
        .I4(Q[7]),
        .I5(Q[6]),
        .O(access_is_fix_q_reg));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFE)) 
    \m_axi_awlen[7]_INST_0_i_15 
       (.I0(Q[7]),
        .I1(Q[6]),
        .I2(\m_axi_awlen[7]_INST_0_i_19_n_0 ),
        .I3(\m_axi_awlen[7]_INST_0_i_20_n_0 ),
        .I4(\gpr1.dout_i_reg[1] [3]),
        .I5(Q[3]),
        .O(\pushed_commands_reg[7] ));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT4 #(
    .INIT(16'hFFF6)) 
    \m_axi_awlen[7]_INST_0_i_17 
       (.I0(\gpr1.dout_i_reg[1]_0 [3]),
        .I1(Q[3]),
        .I2(Q[5]),
        .I3(Q[4]),
        .O(\m_axi_awlen[7]_INST_0_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \m_axi_awlen[7]_INST_0_i_18 
       (.I0(\gpr1.dout_i_reg[1]_0 [1]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\gpr1.dout_i_reg[1]_0 [0]),
        .I4(Q[2]),
        .I5(\gpr1.dout_i_reg[1]_0 [2]),
        .O(\m_axi_awlen[7]_INST_0_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \m_axi_awlen[7]_INST_0_i_19 
       (.I0(\gpr1.dout_i_reg[1] [0]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\gpr1.dout_i_reg[1] [1]),
        .I4(Q[2]),
        .I5(\gpr1.dout_i_reg[1] [2]),
        .O(\m_axi_awlen[7]_INST_0_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \m_axi_awlen[7]_INST_0_i_20 
       (.I0(Q[4]),
        .I1(Q[5]),
        .O(\m_axi_awlen[7]_INST_0_i_20_n_0 ));
endmodule

(* ORIG_REF_NAME = "axi_data_fifo_v2_1_28_fifo_gen" *) 
module design_1_auto_ds_0_axi_data_fifo_v2_1_28_fifo_gen__parameterized0
   (dout,
    din,
    E,
    D,
    s_axi_arvalid_0,
    m_axi_arready_0,
    command_ongoing_reg,
    cmd_push_block_reg,
    cmd_push_block_reg_0,
    cmd_push_block_reg_1,
    m_axi_rvalid_0,
    m_axi_rvalid_1,
    m_axi_rvalid_2,
    m_axi_rvalid_3,
    s_axi_rdata,
    m_axi_arready_1,
    split_ongoing_reg,
    access_is_wrap_q_reg,
    s_axi_aresetn,
    s_axi_rvalid,
    m_axi_rvalid_4,
    m_axi_rready,
    \goreg_dm.dout_i_reg[17] ,
    \goreg_dm.dout_i_reg[2] ,
    s_axi_rlast,
    CLK,
    SR,
    \m_axi_arsize[0] ,
    Q,
    fix_need_to_split_q,
    \m_axi_arlen[7]_INST_0_i_1_0 ,
    access_is_wrap_q,
    split_ongoing,
    s_axi_arvalid,
    command_ongoing_reg_0,
    areset_d,
    command_ongoing,
    m_axi_arready,
    cmd_push_block,
    out,
    cmd_empty_reg,
    cmd_empty,
    m_axi_rvalid,
    s_axi_rvalid_0,
    s_axi_rready,
    \WORD_LANE[3].S_AXI_RDATA_II_reg[127] ,
    m_axi_rdata,
    p_3_in,
    m_axi_arvalid,
    s_axi_rid,
    access_is_fix_q,
    incr_need_to_split_q,
    wrap_need_to_split_q,
    \m_axi_arlen[7] ,
    \m_axi_arlen[7]_0 ,
    \m_axi_arlen[7]_INST_0_i_1_1 ,
    \m_axi_arlen[4] ,
    access_is_incr_q,
    \m_axi_arlen[7]_INST_0_i_10_0 ,
    \m_axi_arlen[7]_INST_0_i_10_1 ,
    \gpr1.dout_i_reg[15] ,
    si_full_size_q,
    \gpr1.dout_i_reg[15]_0 ,
    \gpr1.dout_i_reg[15]_1 ,
    \gpr1.dout_i_reg[15]_2 ,
    \gpr1.dout_i_reg[15]_3 ,
    \m_axi_arlen[4]_INST_0_i_3_0 ,
    legal_wrap_len_q,
    \S_AXI_RRESP_ACC_reg[0] ,
    \current_word_1_reg[1] ,
    \S_AXI_RRESP_ACC_reg[0]_0 ,
    \current_word_1_reg[2] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1_reg[3] ,
    first_mi_word,
    \current_word_1_reg[3]_0 ,
    \s_axi_rdata[127]_INST_0_i_2_0 ,
    m_axi_rlast);
  output [19:0]dout;
  output [11:0]din;
  output [0:0]E;
  output [4:0]D;
  output s_axi_arvalid_0;
  output m_axi_arready_0;
  output command_ongoing_reg;
  output cmd_push_block_reg;
  output [0:0]cmd_push_block_reg_0;
  output cmd_push_block_reg_1;
  output [0:0]m_axi_rvalid_0;
  output [0:0]m_axi_rvalid_1;
  output [0:0]m_axi_rvalid_2;
  output [0:0]m_axi_rvalid_3;
  output [127:0]s_axi_rdata;
  output [0:0]m_axi_arready_1;
  output split_ongoing_reg;
  output access_is_wrap_q_reg;
  output [0:0]s_axi_aresetn;
  output s_axi_rvalid;
  output [0:0]m_axi_rvalid_4;
  output m_axi_rready;
  output [3:0]\goreg_dm.dout_i_reg[17] ;
  output \goreg_dm.dout_i_reg[2] ;
  output s_axi_rlast;
  input CLK;
  input [0:0]SR;
  input [7:0]\m_axi_arsize[0] ;
  input [5:0]Q;
  input fix_need_to_split_q;
  input [7:0]\m_axi_arlen[7]_INST_0_i_1_0 ;
  input access_is_wrap_q;
  input split_ongoing;
  input s_axi_arvalid;
  input [0:0]command_ongoing_reg_0;
  input [1:0]areset_d;
  input command_ongoing;
  input m_axi_arready;
  input cmd_push_block;
  input out;
  input cmd_empty_reg;
  input cmd_empty;
  input m_axi_rvalid;
  input s_axi_rvalid_0;
  input s_axi_rready;
  input \WORD_LANE[3].S_AXI_RDATA_II_reg[127] ;
  input [31:0]m_axi_rdata;
  input [127:0]p_3_in;
  input [15:0]m_axi_arvalid;
  input [15:0]s_axi_rid;
  input access_is_fix_q;
  input incr_need_to_split_q;
  input wrap_need_to_split_q;
  input [7:0]\m_axi_arlen[7] ;
  input [7:0]\m_axi_arlen[7]_0 ;
  input [7:0]\m_axi_arlen[7]_INST_0_i_1_1 ;
  input [4:0]\m_axi_arlen[4] ;
  input access_is_incr_q;
  input [7:0]\m_axi_arlen[7]_INST_0_i_10_0 ;
  input [3:0]\m_axi_arlen[7]_INST_0_i_10_1 ;
  input \gpr1.dout_i_reg[15] ;
  input si_full_size_q;
  input [1:0]\gpr1.dout_i_reg[15]_0 ;
  input [3:0]\gpr1.dout_i_reg[15]_1 ;
  input \gpr1.dout_i_reg[15]_2 ;
  input \gpr1.dout_i_reg[15]_3 ;
  input [4:0]\m_axi_arlen[4]_INST_0_i_3_0 ;
  input legal_wrap_len_q;
  input \S_AXI_RRESP_ACC_reg[0] ;
  input \current_word_1_reg[1] ;
  input \S_AXI_RRESP_ACC_reg[0]_0 ;
  input \current_word_1_reg[2] ;
  input \current_word_1_reg[1]_0 ;
  input [1:0]\current_word_1_reg[3] ;
  input first_mi_word;
  input \current_word_1_reg[3]_0 ;
  input \s_axi_rdata[127]_INST_0_i_2_0 ;
  input m_axi_rlast;

  wire CLK;
  wire [4:0]D;
  wire [0:0]E;
  wire [5:0]Q;
  wire [0:0]SR;
  wire \S_AXI_RRESP_ACC_reg[0] ;
  wire \S_AXI_RRESP_ACC_reg[0]_0 ;
  wire [3:0]\USE_READ.rd_cmd_mask ;
  wire [3:3]\USE_READ.rd_cmd_offset ;
  wire \USE_READ.rd_cmd_ready ;
  wire [2:0]\USE_READ.rd_cmd_size ;
  wire \USE_READ.rd_cmd_split ;
  wire \WORD_LANE[3].S_AXI_RDATA_II_reg[127] ;
  wire access_is_fix_q;
  wire access_is_incr_q;
  wire access_is_wrap_q;
  wire access_is_wrap_q_reg;
  wire [1:0]areset_d;
  wire \cmd_depth[5]_i_3_n_0 ;
  wire cmd_empty;
  wire cmd_empty0;
  wire cmd_empty_reg;
  wire cmd_push_block;
  wire cmd_push_block_reg;
  wire [0:0]cmd_push_block_reg_0;
  wire cmd_push_block_reg_1;
  wire command_ongoing;
  wire command_ongoing_reg;
  wire [0:0]command_ongoing_reg_0;
  wire \current_word_1[2]_i_2_n_0 ;
  wire \current_word_1_reg[1] ;
  wire \current_word_1_reg[1]_0 ;
  wire \current_word_1_reg[2] ;
  wire [1:0]\current_word_1_reg[3] ;
  wire \current_word_1_reg[3]_0 ;
  wire [11:0]din;
  wire [19:0]dout;
  wire empty;
  wire fifo_gen_inst_i_12__0_n_0;
  wire fifo_gen_inst_i_13__0_n_0;
  wire fifo_gen_inst_i_14__0_n_0;
  wire first_mi_word;
  wire fix_need_to_split_q;
  wire full;
  wire [3:0]\goreg_dm.dout_i_reg[17] ;
  wire \goreg_dm.dout_i_reg[2] ;
  wire \gpr1.dout_i_reg[15] ;
  wire [1:0]\gpr1.dout_i_reg[15]_0 ;
  wire [3:0]\gpr1.dout_i_reg[15]_1 ;
  wire \gpr1.dout_i_reg[15]_2 ;
  wire \gpr1.dout_i_reg[15]_3 ;
  wire incr_need_to_split_q;
  wire legal_wrap_len_q;
  wire \m_axi_arlen[0]_INST_0_i_1_n_0 ;
  wire \m_axi_arlen[1]_INST_0_i_1_n_0 ;
  wire \m_axi_arlen[1]_INST_0_i_2_n_0 ;
  wire \m_axi_arlen[1]_INST_0_i_3_n_0 ;
  wire \m_axi_arlen[1]_INST_0_i_4_n_0 ;
  wire \m_axi_arlen[1]_INST_0_i_5_n_0 ;
  wire \m_axi_arlen[2]_INST_0_i_1_n_0 ;
  wire \m_axi_arlen[2]_INST_0_i_2_n_0 ;
  wire \m_axi_arlen[2]_INST_0_i_3_n_0 ;
  wire \m_axi_arlen[3]_INST_0_i_1_n_0 ;
  wire \m_axi_arlen[3]_INST_0_i_2_n_0 ;
  wire \m_axi_arlen[3]_INST_0_i_3_n_0 ;
  wire \m_axi_arlen[3]_INST_0_i_4_n_0 ;
  wire \m_axi_arlen[3]_INST_0_i_5_n_0 ;
  wire [4:0]\m_axi_arlen[4] ;
  wire \m_axi_arlen[4]_INST_0_i_1_n_0 ;
  wire \m_axi_arlen[4]_INST_0_i_2_n_0 ;
  wire [4:0]\m_axi_arlen[4]_INST_0_i_3_0 ;
  wire \m_axi_arlen[4]_INST_0_i_3_n_0 ;
  wire \m_axi_arlen[4]_INST_0_i_4_n_0 ;
  wire \m_axi_arlen[6]_INST_0_i_1_n_0 ;
  wire [7:0]\m_axi_arlen[7] ;
  wire [7:0]\m_axi_arlen[7]_0 ;
  wire [7:0]\m_axi_arlen[7]_INST_0_i_10_0 ;
  wire [3:0]\m_axi_arlen[7]_INST_0_i_10_1 ;
  wire \m_axi_arlen[7]_INST_0_i_10_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_11_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_12_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_13_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_14_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_15_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_16_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_17_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_18_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_19_n_0 ;
  wire [7:0]\m_axi_arlen[7]_INST_0_i_1_0 ;
  wire [7:0]\m_axi_arlen[7]_INST_0_i_1_1 ;
  wire \m_axi_arlen[7]_INST_0_i_1_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_20_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_2_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_3_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_4_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_5_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_6_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_7_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_8_n_0 ;
  wire \m_axi_arlen[7]_INST_0_i_9_n_0 ;
  wire m_axi_arready;
  wire m_axi_arready_0;
  wire [0:0]m_axi_arready_1;
  wire [7:0]\m_axi_arsize[0] ;
  wire [15:0]m_axi_arvalid;
  wire m_axi_arvalid_INST_0_i_1_n_0;
  wire m_axi_arvalid_INST_0_i_2_n_0;
  wire m_axi_arvalid_INST_0_i_3_n_0;
  wire m_axi_arvalid_INST_0_i_4_n_0;
  wire m_axi_arvalid_INST_0_i_5_n_0;
  wire m_axi_arvalid_INST_0_i_6_n_0;
  wire [31:0]m_axi_rdata;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire m_axi_rready_INST_0_i_1_n_0;
  wire m_axi_rready_INST_0_i_2_n_0;
  wire m_axi_rvalid;
  wire [0:0]m_axi_rvalid_0;
  wire [0:0]m_axi_rvalid_1;
  wire [0:0]m_axi_rvalid_2;
  wire [0:0]m_axi_rvalid_3;
  wire [0:0]m_axi_rvalid_4;
  wire out;
  wire [28:18]p_0_out;
  wire [127:0]p_3_in;
  wire [0:0]s_axi_aresetn;
  wire s_axi_arvalid;
  wire s_axi_arvalid_0;
  wire [127:0]s_axi_rdata;
  wire \s_axi_rdata[127]_INST_0_i_2_0 ;
  wire \s_axi_rdata[127]_INST_0_i_2_n_0 ;
  wire \s_axi_rdata[127]_INST_0_i_6_n_0 ;
  wire [15:0]s_axi_rid;
  wire s_axi_rlast;
  wire s_axi_rready;
  wire \s_axi_rresp[1]_INST_0_i_2_n_0 ;
  wire \s_axi_rresp[1]_INST_0_i_3_n_0 ;
  wire s_axi_rvalid;
  wire s_axi_rvalid_0;
  wire s_axi_rvalid_INST_0_i_2_n_0;
  wire s_axi_rvalid_INST_0_i_4_n_0;
  wire si_full_size_q;
  wire split_ongoing;
  wire split_ongoing_reg;
  wire wrap_need_to_split_q;
  wire NLW_fifo_gen_inst_almost_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_almost_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED;
  wire NLW_fifo_gen_inst_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_valid_UNCONNECTED;
  wire NLW_fifo_gen_inst_wr_ack_UNCONNECTED;
  wire NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_data_count_UNCONNECTED;
  wire [31:0]NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED;
  wire [31:0]NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_rd_data_count_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_wr_data_count_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'h08)) 
    S_AXI_AREADY_I_i_2__0
       (.I0(m_axi_arready),
        .I1(command_ongoing_reg),
        .I2(fifo_gen_inst_i_12__0_n_0),
        .O(m_axi_arready_0));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT5 #(
    .INIT(32'h55755555)) 
    \WORD_LANE[0].S_AXI_RDATA_II[31]_i_1 
       (.I0(out),
        .I1(m_axi_rready_INST_0_i_1_n_0),
        .I2(m_axi_rvalid),
        .I3(empty),
        .I4(s_axi_rready),
        .O(s_axi_aresetn));
  LUT6 #(
    .INIT(64'h000000A800000000)) 
    \WORD_LANE[0].S_AXI_RDATA_II[31]_i_2 
       (.I0(m_axi_rvalid),
        .I1(s_axi_rready),
        .I2(m_axi_rready_INST_0_i_1_n_0),
        .I3(empty),
        .I4(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I5(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .O(m_axi_rvalid_3));
  LUT6 #(
    .INIT(64'h00000000000000A8)) 
    \WORD_LANE[1].S_AXI_RDATA_II[63]_i_1 
       (.I0(m_axi_rvalid),
        .I1(s_axi_rready),
        .I2(m_axi_rready_INST_0_i_1_n_0),
        .I3(empty),
        .I4(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I5(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .O(m_axi_rvalid_2));
  LUT6 #(
    .INIT(64'h00A8000000000000)) 
    \WORD_LANE[2].S_AXI_RDATA_II[95]_i_1 
       (.I0(m_axi_rvalid),
        .I1(s_axi_rready),
        .I2(m_axi_rready_INST_0_i_1_n_0),
        .I3(empty),
        .I4(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I5(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .O(m_axi_rvalid_1));
  LUT6 #(
    .INIT(64'h000000A800000000)) 
    \WORD_LANE[3].S_AXI_RDATA_II[127]_i_1 
       (.I0(m_axi_rvalid),
        .I1(s_axi_rready),
        .I2(m_axi_rready_INST_0_i_1_n_0),
        .I3(empty),
        .I4(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I5(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .O(m_axi_rvalid_0));
  LUT3 #(
    .INIT(8'h69)) 
    \cmd_depth[1]_i_1 
       (.I0(Q[0]),
        .I1(cmd_empty0),
        .I2(Q[1]),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT4 #(
    .INIT(16'h78E1)) 
    \cmd_depth[2]_i_1 
       (.I0(cmd_empty0),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT5 #(
    .INIT(32'h7FFE8001)) 
    \cmd_depth[3]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(cmd_empty0),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAA9)) 
    \cmd_depth[4]_i_1 
       (.I0(Q[4]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(cmd_empty0),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \cmd_depth[4]_i_2 
       (.I0(command_ongoing_reg),
        .I1(cmd_push_block),
        .I2(\USE_READ.rd_cmd_ready ),
        .O(cmd_empty0));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \cmd_depth[5]_i_1 
       (.I0(command_ongoing_reg),
        .I1(cmd_push_block),
        .I2(\USE_READ.rd_cmd_ready ),
        .O(cmd_push_block_reg_0));
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \cmd_depth[5]_i_2 
       (.I0(Q[5]),
        .I1(Q[4]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\cmd_depth[5]_i_3_n_0 ),
        .O(D[4]));
  LUT6 #(
    .INIT(64'h02000000FFFFFF02)) 
    \cmd_depth[5]_i_3 
       (.I0(command_ongoing_reg),
        .I1(cmd_push_block),
        .I2(\USE_READ.rd_cmd_ready ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\cmd_depth[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT5 #(
    .INIT(32'hF2DDD000)) 
    cmd_empty_i_1
       (.I0(command_ongoing_reg),
        .I1(cmd_push_block),
        .I2(cmd_empty_reg),
        .I3(\USE_READ.rd_cmd_ready ),
        .I4(cmd_empty),
        .O(cmd_push_block_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT4 #(
    .INIT(16'h4E00)) 
    cmd_push_block_i_1__0
       (.I0(command_ongoing_reg),
        .I1(cmd_push_block),
        .I2(m_axi_arready),
        .I3(out),
        .O(cmd_push_block_reg));
  LUT6 #(
    .INIT(64'h8FFF8F8F88008888)) 
    command_ongoing_i_1__0
       (.I0(s_axi_arvalid),
        .I1(command_ongoing_reg_0),
        .I2(m_axi_arready_0),
        .I3(areset_d[0]),
        .I4(areset_d[1]),
        .I5(command_ongoing),
        .O(s_axi_arvalid_0));
  LUT5 #(
    .INIT(32'h88888882)) 
    \current_word_1[0]_i_1 
       (.I0(\USE_READ.rd_cmd_mask [0]),
        .I1(\current_word_1_reg[1] ),
        .I2(dout[9]),
        .I3(dout[10]),
        .I4(dout[8]),
        .O(\goreg_dm.dout_i_reg[17] [0]));
  LUT6 #(
    .INIT(64'h8888828288888288)) 
    \current_word_1[1]_i_1 
       (.I0(\USE_READ.rd_cmd_mask [1]),
        .I1(\current_word_1_reg[1]_0 ),
        .I2(dout[10]),
        .I3(dout[8]),
        .I4(dout[9]),
        .I5(\current_word_1_reg[1] ),
        .O(\goreg_dm.dout_i_reg[17] [1]));
  LUT6 #(
    .INIT(64'h2228222288828888)) 
    \current_word_1[2]_i_1 
       (.I0(\USE_READ.rd_cmd_mask [2]),
        .I1(\current_word_1_reg[2] ),
        .I2(dout[8]),
        .I3(dout[10]),
        .I4(dout[9]),
        .I5(\current_word_1[2]_i_2_n_0 ),
        .O(\goreg_dm.dout_i_reg[17] [2]));
  LUT5 #(
    .INIT(32'h00220020)) 
    \current_word_1[2]_i_2 
       (.I0(\current_word_1_reg[1]_0 ),
        .I1(dout[9]),
        .I2(dout[8]),
        .I3(dout[10]),
        .I4(\current_word_1_reg[1] ),
        .O(\current_word_1[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0002AAA2AAA80008)) 
    \current_word_1[3]_i_1 
       (.I0(\USE_READ.rd_cmd_mask [3]),
        .I1(\current_word_1_reg[3] [1]),
        .I2(first_mi_word),
        .I3(dout[19]),
        .I4(dout[17]),
        .I5(\current_word_1_reg[3]_0 ),
        .O(\goreg_dm.dout_i_reg[17] [3]));
  (* C_ADD_NGC_CONSTRAINT = "0" *) 
  (* C_APPLICATION_TYPE_AXIS = "0" *) 
  (* C_APPLICATION_TYPE_RACH = "0" *) 
  (* C_APPLICATION_TYPE_RDCH = "0" *) 
  (* C_APPLICATION_TYPE_WACH = "0" *) 
  (* C_APPLICATION_TYPE_WDCH = "0" *) 
  (* C_APPLICATION_TYPE_WRCH = "0" *) 
  (* C_AXIS_TDATA_WIDTH = "64" *) 
  (* C_AXIS_TDEST_WIDTH = "4" *) 
  (* C_AXIS_TID_WIDTH = "8" *) 
  (* C_AXIS_TKEEP_WIDTH = "4" *) 
  (* C_AXIS_TSTRB_WIDTH = "4" *) 
  (* C_AXIS_TUSER_WIDTH = "4" *) 
  (* C_AXIS_TYPE = "0" *) 
  (* C_AXI_ADDR_WIDTH = "32" *) 
  (* C_AXI_ARUSER_WIDTH = "1" *) 
  (* C_AXI_AWUSER_WIDTH = "1" *) 
  (* C_AXI_BUSER_WIDTH = "1" *) 
  (* C_AXI_DATA_WIDTH = "64" *) 
  (* C_AXI_ID_WIDTH = "4" *) 
  (* C_AXI_LEN_WIDTH = "8" *) 
  (* C_AXI_LOCK_WIDTH = "2" *) 
  (* C_AXI_RUSER_WIDTH = "1" *) 
  (* C_AXI_TYPE = "0" *) 
  (* C_AXI_WUSER_WIDTH = "1" *) 
  (* C_COMMON_CLOCK = "1" *) 
  (* C_COUNT_TYPE = "0" *) 
  (* C_DATA_COUNT_WIDTH = "6" *) 
  (* C_DEFAULT_VALUE = "BlankString" *) 
  (* C_DIN_WIDTH = "29" *) 
  (* C_DIN_WIDTH_AXIS = "1" *) 
  (* C_DIN_WIDTH_RACH = "32" *) 
  (* C_DIN_WIDTH_RDCH = "64" *) 
  (* C_DIN_WIDTH_WACH = "32" *) 
  (* C_DIN_WIDTH_WDCH = "64" *) 
  (* C_DIN_WIDTH_WRCH = "2" *) 
  (* C_DOUT_RST_VAL = "0" *) 
  (* C_DOUT_WIDTH = "29" *) 
  (* C_ENABLE_RLOCS = "0" *) 
  (* C_ENABLE_RST_SYNC = "1" *) 
  (* C_EN_SAFETY_CKT = "0" *) 
  (* C_ERROR_INJECTION_TYPE = "0" *) 
  (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) 
  (* C_FAMILY = "zynquplus" *) 
  (* C_FULL_FLAGS_RST_VAL = "0" *) 
  (* C_HAS_ALMOST_EMPTY = "0" *) 
  (* C_HAS_ALMOST_FULL = "0" *) 
  (* C_HAS_AXIS_TDATA = "0" *) 
  (* C_HAS_AXIS_TDEST = "0" *) 
  (* C_HAS_AXIS_TID = "0" *) 
  (* C_HAS_AXIS_TKEEP = "0" *) 
  (* C_HAS_AXIS_TLAST = "0" *) 
  (* C_HAS_AXIS_TREADY = "1" *) 
  (* C_HAS_AXIS_TSTRB = "0" *) 
  (* C_HAS_AXIS_TUSER = "0" *) 
  (* C_HAS_AXI_ARUSER = "0" *) 
  (* C_HAS_AXI_AWUSER = "0" *) 
  (* C_HAS_AXI_BUSER = "0" *) 
  (* C_HAS_AXI_ID = "0" *) 
  (* C_HAS_AXI_RD_CHANNEL = "0" *) 
  (* C_HAS_AXI_RUSER = "0" *) 
  (* C_HAS_AXI_WR_CHANNEL = "0" *) 
  (* C_HAS_AXI_WUSER = "0" *) 
  (* C_HAS_BACKUP = "0" *) 
  (* C_HAS_DATA_COUNT = "0" *) 
  (* C_HAS_DATA_COUNTS_AXIS = "0" *) 
  (* C_HAS_DATA_COUNTS_RACH = "0" *) 
  (* C_HAS_DATA_COUNTS_RDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WACH = "0" *) 
  (* C_HAS_DATA_COUNTS_WDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WRCH = "0" *) 
  (* C_HAS_INT_CLK = "0" *) 
  (* C_HAS_MASTER_CE = "0" *) 
  (* C_HAS_MEMINIT_FILE = "0" *) 
  (* C_HAS_OVERFLOW = "0" *) 
  (* C_HAS_PROG_FLAGS_AXIS = "0" *) 
  (* C_HAS_PROG_FLAGS_RACH = "0" *) 
  (* C_HAS_PROG_FLAGS_RDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WACH = "0" *) 
  (* C_HAS_PROG_FLAGS_WDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WRCH = "0" *) 
  (* C_HAS_RD_DATA_COUNT = "0" *) 
  (* C_HAS_RD_RST = "0" *) 
  (* C_HAS_RST = "1" *) 
  (* C_HAS_SLAVE_CE = "0" *) 
  (* C_HAS_SRST = "0" *) 
  (* C_HAS_UNDERFLOW = "0" *) 
  (* C_HAS_VALID = "0" *) 
  (* C_HAS_WR_ACK = "0" *) 
  (* C_HAS_WR_DATA_COUNT = "0" *) 
  (* C_HAS_WR_RST = "0" *) 
  (* C_IMPLEMENTATION_TYPE = "0" *) 
  (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RACH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WACH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) 
  (* C_INIT_WR_PNTR_VAL = "0" *) 
  (* C_INTERFACE_TYPE = "0" *) 
  (* C_MEMORY_TYPE = "2" *) 
  (* C_MIF_FILE_NAME = "BlankString" *) 
  (* C_MSGON_VAL = "1" *) 
  (* C_OPTIMIZATION_MODE = "0" *) 
  (* C_OVERFLOW_LOW = "0" *) 
  (* C_POWER_SAVING_MODE = "0" *) 
  (* C_PRELOAD_LATENCY = "0" *) 
  (* C_PRELOAD_REGS = "1" *) 
  (* C_PRIM_FIFO_TYPE = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) 
  (* C_PROG_EMPTY_TYPE = "0" *) 
  (* C_PROG_EMPTY_TYPE_AXIS = "0" *) 
  (* C_PROG_EMPTY_TYPE_RACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_RDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WRCH = "0" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL = "31" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) 
  (* C_PROG_FULL_THRESH_NEGATE_VAL = "30" *) 
  (* C_PROG_FULL_TYPE = "0" *) 
  (* C_PROG_FULL_TYPE_AXIS = "0" *) 
  (* C_PROG_FULL_TYPE_RACH = "0" *) 
  (* C_PROG_FULL_TYPE_RDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WACH = "0" *) 
  (* C_PROG_FULL_TYPE_WDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WRCH = "0" *) 
  (* C_RACH_TYPE = "0" *) 
  (* C_RDCH_TYPE = "0" *) 
  (* C_RD_DATA_COUNT_WIDTH = "6" *) 
  (* C_RD_DEPTH = "32" *) 
  (* C_RD_FREQ = "1" *) 
  (* C_RD_PNTR_WIDTH = "5" *) 
  (* C_REG_SLICE_MODE_AXIS = "0" *) 
  (* C_REG_SLICE_MODE_RACH = "0" *) 
  (* C_REG_SLICE_MODE_RDCH = "0" *) 
  (* C_REG_SLICE_MODE_WACH = "0" *) 
  (* C_REG_SLICE_MODE_WDCH = "0" *) 
  (* C_REG_SLICE_MODE_WRCH = "0" *) 
  (* C_SELECT_XPM = "0" *) 
  (* C_SYNCHRONIZER_STAGE = "3" *) 
  (* C_UNDERFLOW_LOW = "0" *) 
  (* C_USE_COMMON_OVERFLOW = "0" *) 
  (* C_USE_COMMON_UNDERFLOW = "0" *) 
  (* C_USE_DEFAULT_SETTINGS = "0" *) 
  (* C_USE_DOUT_RST = "0" *) 
  (* C_USE_ECC = "0" *) 
  (* C_USE_ECC_AXIS = "0" *) 
  (* C_USE_ECC_RACH = "0" *) 
  (* C_USE_ECC_RDCH = "0" *) 
  (* C_USE_ECC_WACH = "0" *) 
  (* C_USE_ECC_WDCH = "0" *) 
  (* C_USE_ECC_WRCH = "0" *) 
  (* C_USE_EMBEDDED_REG = "0" *) 
  (* C_USE_FIFO16_FLAGS = "0" *) 
  (* C_USE_FWFT_DATA_COUNT = "1" *) 
  (* C_USE_PIPELINE_REG = "0" *) 
  (* C_VALID_LOW = "0" *) 
  (* C_WACH_TYPE = "0" *) 
  (* C_WDCH_TYPE = "0" *) 
  (* C_WRCH_TYPE = "0" *) 
  (* C_WR_ACK_LOW = "0" *) 
  (* C_WR_DATA_COUNT_WIDTH = "6" *) 
  (* C_WR_DEPTH = "32" *) 
  (* C_WR_DEPTH_AXIS = "1024" *) 
  (* C_WR_DEPTH_RACH = "16" *) 
  (* C_WR_DEPTH_RDCH = "1024" *) 
  (* C_WR_DEPTH_WACH = "16" *) 
  (* C_WR_DEPTH_WDCH = "1024" *) 
  (* C_WR_DEPTH_WRCH = "16" *) 
  (* C_WR_FREQ = "1" *) 
  (* C_WR_PNTR_WIDTH = "5" *) 
  (* C_WR_PNTR_WIDTH_AXIS = "10" *) 
  (* C_WR_PNTR_WIDTH_RACH = "4" *) 
  (* C_WR_PNTR_WIDTH_RDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WACH = "4" *) 
  (* C_WR_PNTR_WIDTH_WDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WRCH = "4" *) 
  (* C_WR_RESPONSE_LATENCY = "1" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* is_du_within_envelope = "true" *) 
  design_1_auto_ds_0_fifo_generator_v13_2_9__parameterized0 fifo_gen_inst
       (.almost_empty(NLW_fifo_gen_inst_almost_empty_UNCONNECTED),
        .almost_full(NLW_fifo_gen_inst_almost_full_UNCONNECTED),
        .axi_ar_data_count(NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED[4:0]),
        .axi_ar_dbiterr(NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED),
        .axi_ar_injectdbiterr(1'b0),
        .axi_ar_injectsbiterr(1'b0),
        .axi_ar_overflow(NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED),
        .axi_ar_prog_empty(NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED),
        .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_prog_full(NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED),
        .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_rd_data_count(NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED[4:0]),
        .axi_ar_sbiterr(NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED),
        .axi_ar_underflow(NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED),
        .axi_ar_wr_data_count(NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED[4:0]),
        .axi_aw_data_count(NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED[4:0]),
        .axi_aw_dbiterr(NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED),
        .axi_aw_injectdbiterr(1'b0),
        .axi_aw_injectsbiterr(1'b0),
        .axi_aw_overflow(NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED),
        .axi_aw_prog_empty(NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED),
        .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_prog_full(NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED),
        .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_rd_data_count(NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED[4:0]),
        .axi_aw_sbiterr(NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED),
        .axi_aw_underflow(NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED),
        .axi_aw_wr_data_count(NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED[4:0]),
        .axi_b_data_count(NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED[4:0]),
        .axi_b_dbiterr(NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED),
        .axi_b_injectdbiterr(1'b0),
        .axi_b_injectsbiterr(1'b0),
        .axi_b_overflow(NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED),
        .axi_b_prog_empty(NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED),
        .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_prog_full(NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED),
        .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_rd_data_count(NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED[4:0]),
        .axi_b_sbiterr(NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED),
        .axi_b_underflow(NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED),
        .axi_b_wr_data_count(NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED[4:0]),
        .axi_r_data_count(NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED[10:0]),
        .axi_r_dbiterr(NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED),
        .axi_r_injectdbiterr(1'b0),
        .axi_r_injectsbiterr(1'b0),
        .axi_r_overflow(NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED),
        .axi_r_prog_empty(NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED),
        .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_prog_full(NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED),
        .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_rd_data_count(NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED[10:0]),
        .axi_r_sbiterr(NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED),
        .axi_r_underflow(NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED),
        .axi_r_wr_data_count(NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED[10:0]),
        .axi_w_data_count(NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED[10:0]),
        .axi_w_dbiterr(NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED),
        .axi_w_injectdbiterr(1'b0),
        .axi_w_injectsbiterr(1'b0),
        .axi_w_overflow(NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED),
        .axi_w_prog_empty(NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED),
        .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_prog_full(NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED),
        .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_rd_data_count(NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED[10:0]),
        .axi_w_sbiterr(NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED),
        .axi_w_underflow(NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED),
        .axi_w_wr_data_count(NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED[10:0]),
        .axis_data_count(NLW_fifo_gen_inst_axis_data_count_UNCONNECTED[10:0]),
        .axis_dbiterr(NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED),
        .axis_injectdbiterr(1'b0),
        .axis_injectsbiterr(1'b0),
        .axis_overflow(NLW_fifo_gen_inst_axis_overflow_UNCONNECTED),
        .axis_prog_empty(NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED),
        .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_prog_full(NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED),
        .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_rd_data_count(NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED[10:0]),
        .axis_sbiterr(NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED),
        .axis_underflow(NLW_fifo_gen_inst_axis_underflow_UNCONNECTED),
        .axis_wr_data_count(NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED[10:0]),
        .backup(1'b0),
        .backup_marker(1'b0),
        .clk(CLK),
        .data_count(NLW_fifo_gen_inst_data_count_UNCONNECTED[5:0]),
        .dbiterr(NLW_fifo_gen_inst_dbiterr_UNCONNECTED),
        .din({p_0_out[28],din[11],\m_axi_arsize[0] [7],p_0_out[25:18],\m_axi_arsize[0] [6:3],din[10:0],\m_axi_arsize[0] [2:0]}),
        .dout({dout[19],\USE_READ.rd_cmd_split ,dout[18:14],\USE_READ.rd_cmd_offset ,dout[13:11],\USE_READ.rd_cmd_mask ,dout[10:0],\USE_READ.rd_cmd_size }),
        .empty(empty),
        .full(full),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .int_clk(1'b0),
        .m_aclk(1'b0),
        .m_aclk_en(1'b0),
        .m_axi_araddr(NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED[31:0]),
        .m_axi_arburst(NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED[1:0]),
        .m_axi_arcache(NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED[3:0]),
        .m_axi_arid(NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED[3:0]),
        .m_axi_arlen(NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED[7:0]),
        .m_axi_arlock(NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED[1:0]),
        .m_axi_arprot(NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED[2:0]),
        .m_axi_arqos(NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED[3:0]),
        .m_axi_arready(1'b0),
        .m_axi_arregion(NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED[3:0]),
        .m_axi_arsize(NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED[2:0]),
        .m_axi_aruser(NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED[0]),
        .m_axi_arvalid(NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED),
        .m_axi_awaddr(NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED[31:0]),
        .m_axi_awburst(NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED[1:0]),
        .m_axi_awcache(NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED[3:0]),
        .m_axi_awid(NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED[3:0]),
        .m_axi_awlen(NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED[7:0]),
        .m_axi_awlock(NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED[1:0]),
        .m_axi_awprot(NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED[2:0]),
        .m_axi_awqos(NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED[3:0]),
        .m_axi_awready(1'b0),
        .m_axi_awregion(NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED[3:0]),
        .m_axi_awsize(NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED[2:0]),
        .m_axi_awuser(NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED[0]),
        .m_axi_awvalid(NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED),
        .m_axi_bid({1'b0,1'b0,1'b0,1'b0}),
        .m_axi_bready(NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED),
        .m_axi_bresp({1'b0,1'b0}),
        .m_axi_buser(1'b0),
        .m_axi_bvalid(1'b0),
        .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rid({1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rlast(1'b0),
        .m_axi_rready(NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED),
        .m_axi_rresp({1'b0,1'b0}),
        .m_axi_ruser(1'b0),
        .m_axi_rvalid(1'b0),
        .m_axi_wdata(NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED[63:0]),
        .m_axi_wid(NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED[3:0]),
        .m_axi_wlast(NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED),
        .m_axi_wready(1'b0),
        .m_axi_wstrb(NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED[7:0]),
        .m_axi_wuser(NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED[0]),
        .m_axi_wvalid(NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED),
        .m_axis_tdata(NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED[63:0]),
        .m_axis_tdest(NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED[3:0]),
        .m_axis_tid(NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED[7:0]),
        .m_axis_tkeep(NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED[3:0]),
        .m_axis_tlast(NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED),
        .m_axis_tready(1'b0),
        .m_axis_tstrb(NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED[3:0]),
        .m_axis_tuser(NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED[3:0]),
        .m_axis_tvalid(NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED),
        .overflow(NLW_fifo_gen_inst_overflow_UNCONNECTED),
        .prog_empty(NLW_fifo_gen_inst_prog_empty_UNCONNECTED),
        .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full(NLW_fifo_gen_inst_prog_full_UNCONNECTED),
        .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rd_clk(1'b0),
        .rd_data_count(NLW_fifo_gen_inst_rd_data_count_UNCONNECTED[5:0]),
        .rd_en(\USE_READ.rd_cmd_ready ),
        .rd_rst(1'b0),
        .rd_rst_busy(NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED),
        .rst(SR),
        .s_aclk(1'b0),
        .s_aclk_en(1'b0),
        .s_aresetn(1'b0),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlock({1'b0,1'b0}),
        .s_axi_arprot({1'b0,1'b0,1'b0}),
        .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED),
        .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_aruser(1'b0),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlock({1'b0,1'b0}),
        .s_axi_awprot({1'b0,1'b0,1'b0}),
        .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED),
        .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awuser(1'b0),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED[3:0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_buser(NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED[0]),
        .s_axi_bvalid(NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED),
        .s_axi_rdata(NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED[63:0]),
        .s_axi_rid(NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED[3:0]),
        .s_axi_rlast(NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_ruser(NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED[0]),
        .s_axi_rvalid(NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wuser(1'b0),
        .s_axi_wvalid(1'b0),
        .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tdest({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tkeep({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tlast(1'b0),
        .s_axis_tready(NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED),
        .s_axis_tstrb({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tvalid(1'b0),
        .sbiterr(NLW_fifo_gen_inst_sbiterr_UNCONNECTED),
        .sleep(1'b0),
        .srst(1'b0),
        .underflow(NLW_fifo_gen_inst_underflow_UNCONNECTED),
        .valid(NLW_fifo_gen_inst_valid_UNCONNECTED),
        .wr_ack(NLW_fifo_gen_inst_wr_ack_UNCONNECTED),
        .wr_clk(1'b0),
        .wr_data_count(NLW_fifo_gen_inst_wr_data_count_UNCONNECTED[5:0]),
        .wr_en(E),
        .wr_rst(1'b0),
        .wr_rst_busy(NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_10__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_2 ),
        .I3(\gpr1.dout_i_reg[15]_1 [0]),
        .I4(access_is_wrap_q_reg),
        .I5(\m_axi_arsize[0] [3]),
        .O(p_0_out[18]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    fifo_gen_inst_i_11__0
       (.I0(empty),
        .I1(m_axi_rvalid),
        .I2(s_axi_rvalid_0),
        .I3(s_axi_rready),
        .O(\USE_READ.rd_cmd_ready ));
  LUT6 #(
    .INIT(64'h00A2A2A200A200A2)) 
    fifo_gen_inst_i_12__0
       (.I0(\m_axi_arlen[7]_INST_0_i_14_n_0 ),
        .I1(access_is_incr_q),
        .I2(\m_axi_arlen[7]_INST_0_i_15_n_0 ),
        .I3(access_is_wrap_q),
        .I4(split_ongoing),
        .I5(wrap_need_to_split_q),
        .O(fifo_gen_inst_i_12__0_n_0));
  LUT6 #(
    .INIT(64'h0040CCCC4444CCCC)) 
    fifo_gen_inst_i_13__0
       (.I0(access_is_wrap_q),
        .I1(\gpr1.dout_i_reg[15]_1 [3]),
        .I2(\gpr1.dout_i_reg[15]_0 [1]),
        .I3(si_full_size_q),
        .I4(split_ongoing),
        .I5(access_is_incr_q),
        .O(fifo_gen_inst_i_13__0_n_0));
  LUT6 #(
    .INIT(64'h0040CCCC4444CCCC)) 
    fifo_gen_inst_i_14__0
       (.I0(access_is_wrap_q),
        .I1(\gpr1.dout_i_reg[15]_1 [2]),
        .I2(\gpr1.dout_i_reg[15]_0 [0]),
        .I3(si_full_size_q),
        .I4(split_ongoing),
        .I5(access_is_incr_q),
        .O(fifo_gen_inst_i_14__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_15
       (.I0(split_ongoing),
        .I1(access_is_incr_q),
        .O(split_ongoing_reg));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_16
       (.I0(access_is_wrap_q),
        .I1(split_ongoing),
        .O(access_is_wrap_q_reg));
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_1__1
       (.I0(access_is_fix_q),
        .I1(\m_axi_arsize[0] [7]),
        .O(p_0_out[28]));
  LUT4 #(
    .INIT(16'hAAA8)) 
    fifo_gen_inst_i_2__0
       (.I0(fifo_gen_inst_i_12__0_n_0),
        .I1(incr_need_to_split_q),
        .I2(wrap_need_to_split_q),
        .I3(fix_need_to_split_q),
        .O(din[11]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'h80)) 
    fifo_gen_inst_i_3__0
       (.I0(fifo_gen_inst_i_13__0_n_0),
        .I1(\m_axi_arsize[0] [6]),
        .I2(\gpr1.dout_i_reg[15] ),
        .O(p_0_out[25]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'h80)) 
    fifo_gen_inst_i_4__0
       (.I0(fifo_gen_inst_i_14__0_n_0),
        .I1(\m_axi_arsize[0] [5]),
        .I2(\gpr1.dout_i_reg[15] ),
        .O(p_0_out[24]));
  LUT6 #(
    .INIT(64'h0070000000000000)) 
    fifo_gen_inst_i_5__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_1 [1]),
        .I3(access_is_wrap_q_reg),
        .I4(\m_axi_arsize[0] [4]),
        .I5(\gpr1.dout_i_reg[15]_3 ),
        .O(p_0_out[23]));
  LUT6 #(
    .INIT(64'h0070000000000000)) 
    fifo_gen_inst_i_6__1
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_1 [0]),
        .I3(access_is_wrap_q_reg),
        .I4(\m_axi_arsize[0] [3]),
        .I5(\gpr1.dout_i_reg[15]_2 ),
        .O(p_0_out[22]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_7__1
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_0 [1]),
        .I3(\gpr1.dout_i_reg[15]_1 [3]),
        .I4(access_is_wrap_q_reg),
        .I5(\m_axi_arsize[0] [6]),
        .O(p_0_out[21]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_8__1
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_0 [0]),
        .I3(\gpr1.dout_i_reg[15]_1 [2]),
        .I4(access_is_wrap_q_reg),
        .I5(\m_axi_arsize[0] [5]),
        .O(p_0_out[20]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_9__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_3 ),
        .I3(\gpr1.dout_i_reg[15]_1 [1]),
        .I4(access_is_wrap_q_reg),
        .I5(\m_axi_arsize[0] [4]),
        .O(p_0_out[19]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT4 #(
    .INIT(16'h00A8)) 
    first_word_i_1__0
       (.I0(m_axi_rvalid),
        .I1(s_axi_rready),
        .I2(m_axi_rready_INST_0_i_1_n_0),
        .I3(empty),
        .O(m_axi_rvalid_4));
  LUT6 #(
    .INIT(64'hF704F7F708FB0808)) 
    \m_axi_arlen[0]_INST_0 
       (.I0(\m_axi_arlen[7] [0]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .I4(\m_axi_arlen[4] [0]),
        .I5(\m_axi_arlen[0]_INST_0_i_1_n_0 ),
        .O(din[0]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_arlen[0]_INST_0_i_1 
       (.I0(\m_axi_arlen[7]_0 [0]),
        .I1(\m_axi_arsize[0] [7]),
        .I2(\m_axi_arlen[7]_INST_0_i_1_1 [0]),
        .I3(\m_axi_arlen[7]_INST_0_i_10_n_0 ),
        .I4(\m_axi_arlen[1]_INST_0_i_3_n_0 ),
        .O(\m_axi_arlen[0]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0BFBF404F4040BFB)) 
    \m_axi_arlen[1]_INST_0 
       (.I0(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .I1(\m_axi_arlen[4] [1]),
        .I2(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_arlen[7] [1]),
        .I4(\m_axi_arlen[1]_INST_0_i_1_n_0 ),
        .I5(\m_axi_arlen[1]_INST_0_i_2_n_0 ),
        .O(din[1]));
  LUT6 #(
    .INIT(64'h00000000001DFF1D)) 
    \m_axi_arlen[1]_INST_0_i_1 
       (.I0(\m_axi_arlen[1]_INST_0_i_3_n_0 ),
        .I1(\m_axi_arlen[7]_INST_0_i_10_n_0 ),
        .I2(\m_axi_arlen[7]_INST_0_i_1_1 [0]),
        .I3(\m_axi_arsize[0] [7]),
        .I4(\m_axi_arlen[7]_0 [0]),
        .I5(\m_axi_arlen[1]_INST_0_i_4_n_0 ),
        .O(\m_axi_arlen[1]_INST_0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h47444777)) 
    \m_axi_arlen[1]_INST_0_i_2 
       (.I0(\m_axi_arlen[7]_0 [1]),
        .I1(\m_axi_arsize[0] [7]),
        .I2(\m_axi_arlen[7]_INST_0_i_1_1 [1]),
        .I3(\m_axi_arlen[7]_INST_0_i_10_n_0 ),
        .I4(\m_axi_arlen[1]_INST_0_i_5_n_0 ),
        .O(\m_axi_arlen[1]_INST_0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_arlen[1]_INST_0_i_3 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_0 [0]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[4]_INST_0_i_3_0 [0]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_arlen[1]_INST_0_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT5 #(
    .INIT(32'hF704F7F7)) 
    \m_axi_arlen[1]_INST_0_i_4 
       (.I0(\m_axi_arlen[7] [0]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .I4(\m_axi_arlen[4] [0]),
        .O(\m_axi_arlen[1]_INST_0_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_arlen[1]_INST_0_i_5 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_0 [1]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[4]_INST_0_i_3_0 [1]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_arlen[1]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h95959A956A6A656A)) 
    \m_axi_arlen[2]_INST_0 
       (.I0(\m_axi_arlen[2]_INST_0_i_1_n_0 ),
        .I1(\m_axi_arlen[7] [2]),
        .I2(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_arlen[4] [2]),
        .I4(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .I5(\m_axi_arlen[2]_INST_0_i_2_n_0 ),
        .O(din[2]));
  LUT6 #(
    .INIT(64'hFFFF88B888B80000)) 
    \m_axi_arlen[2]_INST_0_i_1 
       (.I0(\m_axi_arlen[7] [1]),
        .I1(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
        .I2(\m_axi_arlen[4] [1]),
        .I3(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .I4(\m_axi_arlen[1]_INST_0_i_1_n_0 ),
        .I5(\m_axi_arlen[1]_INST_0_i_2_n_0 ),
        .O(\m_axi_arlen[2]_INST_0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B8B8)) 
    \m_axi_arlen[2]_INST_0_i_2 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_1 [2]),
        .I1(\m_axi_arlen[7]_INST_0_i_10_n_0 ),
        .I2(\m_axi_arlen[2]_INST_0_i_3_n_0 ),
        .I3(\m_axi_arlen[7]_0 [2]),
        .I4(\m_axi_arsize[0] [7]),
        .O(\m_axi_arlen[2]_INST_0_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_arlen[2]_INST_0_i_3 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_0 [2]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[4]_INST_0_i_3_0 [2]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_arlen[2]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h95959A956A6A656A)) 
    \m_axi_arlen[3]_INST_0 
       (.I0(\m_axi_arlen[3]_INST_0_i_1_n_0 ),
        .I1(\m_axi_arlen[7] [3]),
        .I2(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_arlen[4] [3]),
        .I4(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .I5(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
        .O(din[3]));
  LUT5 #(
    .INIT(32'hBBB2B222)) 
    \m_axi_arlen[3]_INST_0_i_1 
       (.I0(\m_axi_arlen[3]_INST_0_i_3_n_0 ),
        .I1(\m_axi_arlen[2]_INST_0_i_2_n_0 ),
        .I2(\m_axi_arlen[1]_INST_0_i_2_n_0 ),
        .I3(\m_axi_arlen[1]_INST_0_i_1_n_0 ),
        .I4(\m_axi_arlen[3]_INST_0_i_4_n_0 ),
        .O(\m_axi_arlen[3]_INST_0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B8B8)) 
    \m_axi_arlen[3]_INST_0_i_2 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_1 [3]),
        .I1(\m_axi_arlen[7]_INST_0_i_10_n_0 ),
        .I2(\m_axi_arlen[3]_INST_0_i_5_n_0 ),
        .I3(\m_axi_arlen[7]_0 [3]),
        .I4(\m_axi_arsize[0] [7]),
        .O(\m_axi_arlen[3]_INST_0_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \m_axi_arlen[3]_INST_0_i_3 
       (.I0(\m_axi_arlen[7] [2]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[4] [2]),
        .I4(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .O(\m_axi_arlen[3]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \m_axi_arlen[3]_INST_0_i_4 
       (.I0(\m_axi_arlen[7] [1]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[4] [1]),
        .I4(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .O(\m_axi_arlen[3]_INST_0_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_arlen[3]_INST_0_i_5 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_0 [3]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[4]_INST_0_i_3_0 [3]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_arlen[3]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h95959A956A6A656A)) 
    \m_axi_arlen[4]_INST_0 
       (.I0(\m_axi_arlen[4]_INST_0_i_1_n_0 ),
        .I1(\m_axi_arlen[7] [4]),
        .I2(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_arlen[4] [4]),
        .I4(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .I5(\m_axi_arlen[4]_INST_0_i_3_n_0 ),
        .O(din[4]));
  LUT6 #(
    .INIT(64'h88B8FFFF000088B8)) 
    \m_axi_arlen[4]_INST_0_i_1 
       (.I0(\m_axi_arlen[7] [3]),
        .I1(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
        .I2(\m_axi_arlen[4] [3]),
        .I3(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .I4(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
        .I5(\m_axi_arlen[3]_INST_0_i_1_n_0 ),
        .O(\m_axi_arlen[4]_INST_0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT5 #(
    .INIT(32'h0000FD0D)) 
    \m_axi_arlen[4]_INST_0_i_2 
       (.I0(access_is_incr_q),
        .I1(\m_axi_arsize[0] [7]),
        .I2(incr_need_to_split_q),
        .I3(split_ongoing),
        .I4(fix_need_to_split_q),
        .O(\m_axi_arlen[4]_INST_0_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B8B8)) 
    \m_axi_arlen[4]_INST_0_i_3 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_1 [4]),
        .I1(\m_axi_arlen[7]_INST_0_i_10_n_0 ),
        .I2(\m_axi_arlen[4]_INST_0_i_4_n_0 ),
        .I3(\m_axi_arlen[7]_0 [4]),
        .I4(\m_axi_arsize[0] [7]),
        .O(\m_axi_arlen[4]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_arlen[4]_INST_0_i_4 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_0 [4]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[4]_INST_0_i_3_0 [4]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_arlen[4]_INST_0_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT5 #(
    .INIT(32'h5955A6AA)) 
    \m_axi_arlen[5]_INST_0 
       (.I0(\m_axi_arlen[7]_INST_0_i_4_n_0 ),
        .I1(\m_axi_arlen[7] [5]),
        .I2(split_ongoing),
        .I3(wrap_need_to_split_q),
        .I4(\m_axi_arlen[7]_INST_0_i_5_n_0 ),
        .O(din[5]));
  LUT6 #(
    .INIT(64'hD42BBBBB2BD44444)) 
    \m_axi_arlen[6]_INST_0 
       (.I0(\m_axi_arlen[7]_INST_0_i_5_n_0 ),
        .I1(\m_axi_arlen[7]_INST_0_i_4_n_0 ),
        .I2(\m_axi_arlen[7] [5]),
        .I3(\m_axi_arlen[7] [6]),
        .I4(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
        .I5(\m_axi_arlen[7]_INST_0_i_6_n_0 ),
        .O(din[6]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \m_axi_arlen[6]_INST_0_i_1 
       (.I0(wrap_need_to_split_q),
        .I1(split_ongoing),
        .O(\m_axi_arlen[6]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h95559995A999AAA9)) 
    \m_axi_arlen[7]_INST_0 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_n_0 ),
        .I1(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
        .I2(\m_axi_arlen[7]_INST_0_i_3_n_0 ),
        .I3(\m_axi_arlen[7]_INST_0_i_4_n_0 ),
        .I4(\m_axi_arlen[7]_INST_0_i_5_n_0 ),
        .I5(\m_axi_arlen[7]_INST_0_i_6_n_0 ),
        .O(din[7]));
  LUT6 #(
    .INIT(64'h202020DFDFDF20DF)) 
    \m_axi_arlen[7]_INST_0_i_1 
       (.I0(wrap_need_to_split_q),
        .I1(split_ongoing),
        .I2(\m_axi_arlen[7] [7]),
        .I3(\m_axi_arlen[7]_INST_0_i_7_n_0 ),
        .I4(\m_axi_arsize[0] [7]),
        .I5(\m_axi_arlen[7]_0 [7]),
        .O(\m_axi_arlen[7]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFAAFFAABFAAFFAA)) 
    \m_axi_arlen[7]_INST_0_i_10 
       (.I0(\m_axi_arlen[7]_INST_0_i_13_n_0 ),
        .I1(incr_need_to_split_q),
        .I2(\m_axi_arlen[7]_INST_0_i_14_n_0 ),
        .I3(access_is_incr_q),
        .I4(\m_axi_arlen[7]_INST_0_i_15_n_0 ),
        .I5(\m_axi_arlen[7]_INST_0_i_16_n_0 ),
        .O(\m_axi_arlen[7]_INST_0_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT4 #(
    .INIT(16'h4555)) 
    \m_axi_arlen[7]_INST_0_i_11 
       (.I0(fix_need_to_split_q),
        .I1(\m_axi_arlen[7]_INST_0_i_1_0 [5]),
        .I2(access_is_wrap_q),
        .I3(split_ongoing),
        .O(\m_axi_arlen[7]_INST_0_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT4 #(
    .INIT(16'h4555)) 
    \m_axi_arlen[7]_INST_0_i_12 
       (.I0(fix_need_to_split_q),
        .I1(\m_axi_arlen[7]_INST_0_i_1_0 [6]),
        .I2(access_is_wrap_q),
        .I3(split_ongoing),
        .O(\m_axi_arlen[7]_INST_0_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \m_axi_arlen[7]_INST_0_i_13 
       (.I0(access_is_wrap_q),
        .I1(legal_wrap_len_q),
        .I2(split_ongoing),
        .O(\m_axi_arlen[7]_INST_0_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hDDDDDDDDDDDDDDD5)) 
    \m_axi_arlen[7]_INST_0_i_14 
       (.I0(access_is_fix_q),
        .I1(fix_need_to_split_q),
        .I2(\m_axi_arlen[7]_INST_0_i_17_n_0 ),
        .I3(\m_axi_arlen[7]_INST_0_i_18_n_0 ),
        .I4(\m_axi_arlen[7]_INST_0_i_10_0 [7]),
        .I5(\m_axi_arlen[7]_INST_0_i_10_0 [6]),
        .O(\m_axi_arlen[7]_INST_0_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFE)) 
    \m_axi_arlen[7]_INST_0_i_15 
       (.I0(\m_axi_arlen[7]_INST_0_i_10_0 [7]),
        .I1(\m_axi_arlen[7]_INST_0_i_10_0 [6]),
        .I2(\m_axi_arlen[7]_INST_0_i_19_n_0 ),
        .I3(\m_axi_arlen[7]_INST_0_i_20_n_0 ),
        .I4(\m_axi_arlen[7]_INST_0_i_10_1 [3]),
        .I5(\m_axi_arlen[7]_INST_0_i_10_0 [3]),
        .O(\m_axi_arlen[7]_INST_0_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \m_axi_arlen[7]_INST_0_i_16 
       (.I0(access_is_wrap_q),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .O(\m_axi_arlen[7]_INST_0_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \m_axi_arlen[7]_INST_0_i_17 
       (.I0(\m_axi_arlen[7]_0 [0]),
        .I1(\m_axi_arlen[7]_INST_0_i_10_0 [0]),
        .I2(\m_axi_arlen[7]_INST_0_i_10_0 [1]),
        .I3(\m_axi_arlen[7]_0 [1]),
        .I4(\m_axi_arlen[7]_INST_0_i_10_0 [2]),
        .I5(\m_axi_arlen[7]_0 [2]),
        .O(\m_axi_arlen[7]_INST_0_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT4 #(
    .INIT(16'hFFF6)) 
    \m_axi_arlen[7]_INST_0_i_18 
       (.I0(\m_axi_arlen[7]_0 [3]),
        .I1(\m_axi_arlen[7]_INST_0_i_10_0 [3]),
        .I2(\m_axi_arlen[7]_INST_0_i_10_0 [5]),
        .I3(\m_axi_arlen[7]_INST_0_i_10_0 [4]),
        .O(\m_axi_arlen[7]_INST_0_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \m_axi_arlen[7]_INST_0_i_19 
       (.I0(\m_axi_arlen[7]_INST_0_i_10_1 [0]),
        .I1(\m_axi_arlen[7]_INST_0_i_10_0 [0]),
        .I2(\m_axi_arlen[7]_INST_0_i_10_0 [2]),
        .I3(\m_axi_arlen[7]_INST_0_i_10_1 [2]),
        .I4(\m_axi_arlen[7]_INST_0_i_10_0 [1]),
        .I5(\m_axi_arlen[7]_INST_0_i_10_1 [1]),
        .O(\m_axi_arlen[7]_INST_0_i_19_n_0 ));
  LUT3 #(
    .INIT(8'h20)) 
    \m_axi_arlen[7]_INST_0_i_2 
       (.I0(\m_axi_arlen[7] [6]),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .O(\m_axi_arlen[7]_INST_0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \m_axi_arlen[7]_INST_0_i_20 
       (.I0(\m_axi_arlen[7]_INST_0_i_10_0 [4]),
        .I1(\m_axi_arlen[7]_INST_0_i_10_0 [5]),
        .O(\m_axi_arlen[7]_INST_0_i_20_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \m_axi_arlen[7]_INST_0_i_3 
       (.I0(\m_axi_arlen[7] [5]),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .O(\m_axi_arlen[7]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hB2BB22B2)) 
    \m_axi_arlen[7]_INST_0_i_4 
       (.I0(\m_axi_arlen[7]_INST_0_i_8_n_0 ),
        .I1(\m_axi_arlen[4]_INST_0_i_3_n_0 ),
        .I2(\m_axi_arlen[3]_INST_0_i_1_n_0 ),
        .I3(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
        .I4(\m_axi_arlen[7]_INST_0_i_9_n_0 ),
        .O(\m_axi_arlen[7]_INST_0_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_arlen[7]_INST_0_i_5 
       (.I0(\m_axi_arlen[7]_0 [5]),
        .I1(\m_axi_arsize[0] [7]),
        .I2(\m_axi_arlen[7]_INST_0_i_1_1 [5]),
        .I3(\m_axi_arlen[7]_INST_0_i_10_n_0 ),
        .I4(\m_axi_arlen[7]_INST_0_i_11_n_0 ),
        .O(\m_axi_arlen[7]_INST_0_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_arlen[7]_INST_0_i_6 
       (.I0(\m_axi_arlen[7]_0 [6]),
        .I1(\m_axi_arsize[0] [7]),
        .I2(\m_axi_arlen[7]_INST_0_i_1_1 [6]),
        .I3(\m_axi_arlen[7]_INST_0_i_10_n_0 ),
        .I4(\m_axi_arlen[7]_INST_0_i_12_n_0 ),
        .O(\m_axi_arlen[7]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h8B888B8B8B8B8B8B)) 
    \m_axi_arlen[7]_INST_0_i_7 
       (.I0(\m_axi_arlen[7]_INST_0_i_1_1 [7]),
        .I1(\m_axi_arlen[7]_INST_0_i_10_n_0 ),
        .I2(fix_need_to_split_q),
        .I3(\m_axi_arlen[7]_INST_0_i_1_0 [7]),
        .I4(access_is_wrap_q),
        .I5(split_ongoing),
        .O(\m_axi_arlen[7]_INST_0_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \m_axi_arlen[7]_INST_0_i_8 
       (.I0(\m_axi_arlen[7] [4]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[4] [4]),
        .I4(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .O(\m_axi_arlen[7]_INST_0_i_8_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \m_axi_arlen[7]_INST_0_i_9 
       (.I0(\m_axi_arlen[7] [3]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_arlen[4] [3]),
        .I4(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
        .O(\m_axi_arlen[7]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_arsize[0]_INST_0 
       (.I0(\m_axi_arsize[0] [7]),
        .I1(\m_axi_arsize[0] [0]),
        .O(din[8]));
  LUT2 #(
    .INIT(4'hB)) 
    \m_axi_arsize[1]_INST_0 
       (.I0(\m_axi_arsize[0] [1]),
        .I1(\m_axi_arsize[0] [7]),
        .O(din[9]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_arsize[2]_INST_0 
       (.I0(\m_axi_arsize[0] [7]),
        .I1(\m_axi_arsize[0] [2]),
        .O(din[10]));
  LUT6 #(
    .INIT(64'h8A8A8A8A88888A88)) 
    m_axi_arvalid_INST_0
       (.I0(command_ongoing),
        .I1(cmd_push_block),
        .I2(full),
        .I3(m_axi_arvalid_INST_0_i_1_n_0),
        .I4(m_axi_arvalid_INST_0_i_2_n_0),
        .I5(cmd_empty),
        .O(command_ongoing_reg));
  LUT6 #(
    .INIT(64'h0001000000000001)) 
    m_axi_arvalid_INST_0_i_1
       (.I0(m_axi_arvalid_INST_0_i_3_n_0),
        .I1(m_axi_arvalid_INST_0_i_4_n_0),
        .I2(m_axi_arvalid_INST_0_i_5_n_0),
        .I3(m_axi_arvalid_INST_0_i_6_n_0),
        .I4(m_axi_arvalid[15]),
        .I5(s_axi_rid[15]),
        .O(m_axi_arvalid_INST_0_i_1_n_0));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    m_axi_arvalid_INST_0_i_2
       (.I0(m_axi_arvalid[12]),
        .I1(s_axi_rid[12]),
        .I2(s_axi_rid[14]),
        .I3(m_axi_arvalid[14]),
        .I4(s_axi_rid[13]),
        .I5(m_axi_arvalid[13]),
        .O(m_axi_arvalid_INST_0_i_2_n_0));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    m_axi_arvalid_INST_0_i_3
       (.I0(s_axi_rid[4]),
        .I1(m_axi_arvalid[4]),
        .I2(s_axi_rid[5]),
        .I3(m_axi_arvalid[5]),
        .I4(m_axi_arvalid[3]),
        .I5(s_axi_rid[3]),
        .O(m_axi_arvalid_INST_0_i_3_n_0));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    m_axi_arvalid_INST_0_i_4
       (.I0(m_axi_arvalid[0]),
        .I1(s_axi_rid[0]),
        .I2(s_axi_rid[2]),
        .I3(m_axi_arvalid[2]),
        .I4(s_axi_rid[1]),
        .I5(m_axi_arvalid[1]),
        .O(m_axi_arvalid_INST_0_i_4_n_0));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    m_axi_arvalid_INST_0_i_5
       (.I0(m_axi_arvalid[9]),
        .I1(s_axi_rid[9]),
        .I2(s_axi_rid[11]),
        .I3(m_axi_arvalid[11]),
        .I4(s_axi_rid[10]),
        .I5(m_axi_arvalid[10]),
        .O(m_axi_arvalid_INST_0_i_5_n_0));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    m_axi_arvalid_INST_0_i_6
       (.I0(m_axi_arvalid[6]),
        .I1(s_axi_rid[6]),
        .I2(s_axi_rid[8]),
        .I3(m_axi_arvalid[8]),
        .I4(s_axi_rid[7]),
        .I5(m_axi_arvalid[7]),
        .O(m_axi_arvalid_INST_0_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'h54)) 
    m_axi_rready_INST_0
       (.I0(empty),
        .I1(m_axi_rready_INST_0_i_1_n_0),
        .I2(s_axi_rready),
        .O(m_axi_rready));
  LUT6 #(
    .INIT(64'h00000000000000EA)) 
    m_axi_rready_INST_0_i_1
       (.I0(m_axi_rready_INST_0_i_2_n_0),
        .I1(\USE_READ.rd_cmd_size [2]),
        .I2(\goreg_dm.dout_i_reg[17] [3]),
        .I3(dout[19]),
        .I4(dout[18]),
        .I5(s_axi_rvalid_0),
        .O(m_axi_rready_INST_0_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFAFFE0EEEAEEE0)) 
    m_axi_rready_INST_0_i_2
       (.I0(\goreg_dm.dout_i_reg[17] [0]),
        .I1(\goreg_dm.dout_i_reg[17] [1]),
        .I2(\USE_READ.rd_cmd_size [1]),
        .I3(\USE_READ.rd_cmd_size [2]),
        .I4(\USE_READ.rd_cmd_size [0]),
        .I5(\goreg_dm.dout_i_reg[17] [2]),
        .O(m_axi_rready_INST_0_i_2_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    \queue_id[15]_i_1__0 
       (.I0(command_ongoing_reg),
        .I1(cmd_push_block),
        .O(E));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[0]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[0]),
        .I4(m_axi_rdata[0]),
        .O(s_axi_rdata[0]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[100]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[4]),
        .I4(p_3_in[100]),
        .O(s_axi_rdata[100]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[101]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[5]),
        .I4(p_3_in[101]),
        .O(s_axi_rdata[101]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[102]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[6]),
        .I4(p_3_in[102]),
        .O(s_axi_rdata[102]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[103]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[7]),
        .I4(p_3_in[103]),
        .O(s_axi_rdata[103]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[104]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[8]),
        .I4(p_3_in[104]),
        .O(s_axi_rdata[104]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[105]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[9]),
        .I4(p_3_in[105]),
        .O(s_axi_rdata[105]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[106]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[10]),
        .I4(p_3_in[106]),
        .O(s_axi_rdata[106]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[107]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[11]),
        .I4(p_3_in[107]),
        .O(s_axi_rdata[107]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[108]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[12]),
        .I4(p_3_in[108]),
        .O(s_axi_rdata[108]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[109]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[13]),
        .I4(p_3_in[109]),
        .O(s_axi_rdata[109]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[10]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[10]),
        .I4(m_axi_rdata[10]),
        .O(s_axi_rdata[10]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[110]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[14]),
        .I4(p_3_in[110]),
        .O(s_axi_rdata[110]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[111]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[15]),
        .I4(p_3_in[111]),
        .O(s_axi_rdata[111]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[112]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[16]),
        .I4(p_3_in[112]),
        .O(s_axi_rdata[112]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[113]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[17]),
        .I4(p_3_in[113]),
        .O(s_axi_rdata[113]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[114]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[18]),
        .I4(p_3_in[114]),
        .O(s_axi_rdata[114]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[115]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[19]),
        .I4(p_3_in[115]),
        .O(s_axi_rdata[115]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[116]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[20]),
        .I4(p_3_in[116]),
        .O(s_axi_rdata[116]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[117]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[21]),
        .I4(p_3_in[117]),
        .O(s_axi_rdata[117]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[118]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[22]),
        .I4(p_3_in[118]),
        .O(s_axi_rdata[118]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[119]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[23]),
        .I4(p_3_in[119]),
        .O(s_axi_rdata[119]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[11]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[11]),
        .I4(m_axi_rdata[11]),
        .O(s_axi_rdata[11]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[120]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[24]),
        .I4(p_3_in[120]),
        .O(s_axi_rdata[120]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[121]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[25]),
        .I4(p_3_in[121]),
        .O(s_axi_rdata[121]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[122]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[26]),
        .I4(p_3_in[122]),
        .O(s_axi_rdata[122]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[123]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[27]),
        .I4(p_3_in[123]),
        .O(s_axi_rdata[123]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[124]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[28]),
        .I4(p_3_in[124]),
        .O(s_axi_rdata[124]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[125]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[29]),
        .I4(p_3_in[125]),
        .O(s_axi_rdata[125]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[126]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[30]),
        .I4(p_3_in[126]),
        .O(s_axi_rdata[126]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[127]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[31]),
        .I4(p_3_in[127]),
        .O(s_axi_rdata[127]));
  LUT5 #(
    .INIT(32'h718E8E71)) 
    \s_axi_rdata[127]_INST_0_i_2 
       (.I0(\current_word_1_reg[2] ),
        .I1(dout[13]),
        .I2(\s_axi_rdata[127]_INST_0_i_6_n_0 ),
        .I3(\S_AXI_RRESP_ACC_reg[0] ),
        .I4(\USE_READ.rd_cmd_offset ),
        .O(\s_axi_rdata[127]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000057F757F7FFFF)) 
    \s_axi_rdata[127]_INST_0_i_6 
       (.I0(dout[11]),
        .I1(dout[14]),
        .I2(\s_axi_rdata[127]_INST_0_i_2_0 ),
        .I3(\current_word_1_reg[3] [0]),
        .I4(dout[12]),
        .I5(\current_word_1_reg[1]_0 ),
        .O(\s_axi_rdata[127]_INST_0_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[12]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[12]),
        .I4(m_axi_rdata[12]),
        .O(s_axi_rdata[12]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[13]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[13]),
        .I4(m_axi_rdata[13]),
        .O(s_axi_rdata[13]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[14]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[14]),
        .I4(m_axi_rdata[14]),
        .O(s_axi_rdata[14]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[15]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[15]),
        .I4(m_axi_rdata[15]),
        .O(s_axi_rdata[15]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[16]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[16]),
        .I4(m_axi_rdata[16]),
        .O(s_axi_rdata[16]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[17]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[17]),
        .I4(m_axi_rdata[17]),
        .O(s_axi_rdata[17]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[18]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[18]),
        .I4(m_axi_rdata[18]),
        .O(s_axi_rdata[18]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[19]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[19]),
        .I4(m_axi_rdata[19]),
        .O(s_axi_rdata[19]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[1]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[1]),
        .I4(m_axi_rdata[1]),
        .O(s_axi_rdata[1]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[20]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[20]),
        .I4(m_axi_rdata[20]),
        .O(s_axi_rdata[20]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[21]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[21]),
        .I4(m_axi_rdata[21]),
        .O(s_axi_rdata[21]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[22]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[22]),
        .I4(m_axi_rdata[22]),
        .O(s_axi_rdata[22]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[23]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[23]),
        .I4(m_axi_rdata[23]),
        .O(s_axi_rdata[23]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[24]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[24]),
        .I4(m_axi_rdata[24]),
        .O(s_axi_rdata[24]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[25]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[25]),
        .I4(m_axi_rdata[25]),
        .O(s_axi_rdata[25]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[26]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[26]),
        .I4(m_axi_rdata[26]),
        .O(s_axi_rdata[26]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[27]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[27]),
        .I4(m_axi_rdata[27]),
        .O(s_axi_rdata[27]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[28]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[28]),
        .I4(m_axi_rdata[28]),
        .O(s_axi_rdata[28]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[29]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[29]),
        .I4(m_axi_rdata[29]),
        .O(s_axi_rdata[29]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[2]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[2]),
        .I4(m_axi_rdata[2]),
        .O(s_axi_rdata[2]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[30]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[30]),
        .I4(m_axi_rdata[30]),
        .O(s_axi_rdata[30]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[31]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[31]),
        .I4(m_axi_rdata[31]),
        .O(s_axi_rdata[31]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[32]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[0]),
        .I4(p_3_in[32]),
        .O(s_axi_rdata[32]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[33]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[1]),
        .I4(p_3_in[33]),
        .O(s_axi_rdata[33]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[34]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[2]),
        .I4(p_3_in[34]),
        .O(s_axi_rdata[34]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[35]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[3]),
        .I4(p_3_in[35]),
        .O(s_axi_rdata[35]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[36]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[4]),
        .I4(p_3_in[36]),
        .O(s_axi_rdata[36]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[37]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[5]),
        .I4(p_3_in[37]),
        .O(s_axi_rdata[37]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[38]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[6]),
        .I4(p_3_in[38]),
        .O(s_axi_rdata[38]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[39]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[7]),
        .I4(p_3_in[39]),
        .O(s_axi_rdata[39]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[3]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[3]),
        .I4(m_axi_rdata[3]),
        .O(s_axi_rdata[3]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[40]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[8]),
        .I4(p_3_in[40]),
        .O(s_axi_rdata[40]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[41]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[9]),
        .I4(p_3_in[41]),
        .O(s_axi_rdata[41]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[42]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[10]),
        .I4(p_3_in[42]),
        .O(s_axi_rdata[42]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[43]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[11]),
        .I4(p_3_in[43]),
        .O(s_axi_rdata[43]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[44]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[12]),
        .I4(p_3_in[44]),
        .O(s_axi_rdata[44]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[45]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[13]),
        .I4(p_3_in[45]),
        .O(s_axi_rdata[45]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[46]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[14]),
        .I4(p_3_in[46]),
        .O(s_axi_rdata[46]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[47]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[15]),
        .I4(p_3_in[47]),
        .O(s_axi_rdata[47]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[48]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[16]),
        .I4(p_3_in[48]),
        .O(s_axi_rdata[48]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[49]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[17]),
        .I4(p_3_in[49]),
        .O(s_axi_rdata[49]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[4]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[4]),
        .I4(m_axi_rdata[4]),
        .O(s_axi_rdata[4]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[50]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[18]),
        .I4(p_3_in[50]),
        .O(s_axi_rdata[50]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[51]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[19]),
        .I4(p_3_in[51]),
        .O(s_axi_rdata[51]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[52]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[20]),
        .I4(p_3_in[52]),
        .O(s_axi_rdata[52]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[53]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[21]),
        .I4(p_3_in[53]),
        .O(s_axi_rdata[53]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[54]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[22]),
        .I4(p_3_in[54]),
        .O(s_axi_rdata[54]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[55]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[23]),
        .I4(p_3_in[55]),
        .O(s_axi_rdata[55]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[56]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[24]),
        .I4(p_3_in[56]),
        .O(s_axi_rdata[56]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[57]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[25]),
        .I4(p_3_in[57]),
        .O(s_axi_rdata[57]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[58]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[26]),
        .I4(p_3_in[58]),
        .O(s_axi_rdata[58]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[59]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[27]),
        .I4(p_3_in[59]),
        .O(s_axi_rdata[59]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[5]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[5]),
        .I4(m_axi_rdata[5]),
        .O(s_axi_rdata[5]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[60]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[28]),
        .I4(p_3_in[60]),
        .O(s_axi_rdata[60]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[61]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[29]),
        .I4(p_3_in[61]),
        .O(s_axi_rdata[61]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[62]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[30]),
        .I4(p_3_in[62]),
        .O(s_axi_rdata[62]));
  LUT5 #(
    .INIT(32'hFF54AB00)) 
    \s_axi_rdata[63]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(m_axi_rdata[31]),
        .I4(p_3_in[63]),
        .O(s_axi_rdata[63]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[64]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[0]),
        .I4(p_3_in[64]),
        .O(s_axi_rdata[64]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[65]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[1]),
        .I4(p_3_in[65]),
        .O(s_axi_rdata[65]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[66]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[2]),
        .I4(p_3_in[66]),
        .O(s_axi_rdata[66]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[67]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[3]),
        .I4(p_3_in[67]),
        .O(s_axi_rdata[67]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[68]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[4]),
        .I4(p_3_in[68]),
        .O(s_axi_rdata[68]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[69]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[5]),
        .I4(p_3_in[69]),
        .O(s_axi_rdata[69]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[6]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[6]),
        .I4(m_axi_rdata[6]),
        .O(s_axi_rdata[6]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[70]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[6]),
        .I4(p_3_in[70]),
        .O(s_axi_rdata[70]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[71]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[7]),
        .I4(p_3_in[71]),
        .O(s_axi_rdata[71]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[72]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[8]),
        .I4(p_3_in[72]),
        .O(s_axi_rdata[72]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[73]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[9]),
        .I4(p_3_in[73]),
        .O(s_axi_rdata[73]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[74]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[10]),
        .I4(p_3_in[74]),
        .O(s_axi_rdata[74]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[75]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[11]),
        .I4(p_3_in[75]),
        .O(s_axi_rdata[75]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[76]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[12]),
        .I4(p_3_in[76]),
        .O(s_axi_rdata[76]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[77]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[13]),
        .I4(p_3_in[77]),
        .O(s_axi_rdata[77]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[78]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[14]),
        .I4(p_3_in[78]),
        .O(s_axi_rdata[78]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[79]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[15]),
        .I4(p_3_in[79]),
        .O(s_axi_rdata[79]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[7]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[7]),
        .I4(m_axi_rdata[7]),
        .O(s_axi_rdata[7]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[80]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[16]),
        .I4(p_3_in[80]),
        .O(s_axi_rdata[80]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[81]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[17]),
        .I4(p_3_in[81]),
        .O(s_axi_rdata[81]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[82]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[18]),
        .I4(p_3_in[82]),
        .O(s_axi_rdata[82]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[83]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[19]),
        .I4(p_3_in[83]),
        .O(s_axi_rdata[83]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[84]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[20]),
        .I4(p_3_in[84]),
        .O(s_axi_rdata[84]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[85]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[21]),
        .I4(p_3_in[85]),
        .O(s_axi_rdata[85]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[86]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[22]),
        .I4(p_3_in[86]),
        .O(s_axi_rdata[86]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[87]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[23]),
        .I4(p_3_in[87]),
        .O(s_axi_rdata[87]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[88]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[24]),
        .I4(p_3_in[88]),
        .O(s_axi_rdata[88]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[89]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[25]),
        .I4(p_3_in[89]),
        .O(s_axi_rdata[89]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[8]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[8]),
        .I4(m_axi_rdata[8]),
        .O(s_axi_rdata[8]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[90]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[26]),
        .I4(p_3_in[90]),
        .O(s_axi_rdata[90]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[91]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[27]),
        .I4(p_3_in[91]),
        .O(s_axi_rdata[91]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[92]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[28]),
        .I4(p_3_in[92]),
        .O(s_axi_rdata[92]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[93]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[29]),
        .I4(p_3_in[93]),
        .O(s_axi_rdata[93]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[94]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[30]),
        .I4(p_3_in[94]),
        .O(s_axi_rdata[94]));
  LUT5 #(
    .INIT(32'hFF15EA00)) 
    \s_axi_rdata[95]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[31]),
        .I4(p_3_in[95]),
        .O(s_axi_rdata[95]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[96]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[0]),
        .I4(p_3_in[96]),
        .O(s_axi_rdata[96]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[97]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[1]),
        .I4(p_3_in[97]),
        .O(s_axi_rdata[97]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[98]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[2]),
        .I4(p_3_in[98]),
        .O(s_axi_rdata[98]));
  LUT5 #(
    .INIT(32'hFF45BA00)) 
    \s_axi_rdata[99]_INST_0 
       (.I0(dout[18]),
        .I1(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I2(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I3(m_axi_rdata[3]),
        .I4(p_3_in[99]),
        .O(s_axi_rdata[99]));
  LUT5 #(
    .INIT(32'hFFBA4500)) 
    \s_axi_rdata[9]_INST_0 
       (.I0(dout[18]),
        .I1(\s_axi_rdata[127]_INST_0_i_2_n_0 ),
        .I2(\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .I3(p_3_in[9]),
        .I4(m_axi_rdata[9]),
        .O(s_axi_rdata[9]));
  LUT2 #(
    .INIT(4'h2)) 
    s_axi_rlast_INST_0
       (.I0(m_axi_rlast),
        .I1(\USE_READ.rd_cmd_split ),
        .O(s_axi_rlast));
  LUT6 #(
    .INIT(64'h00000000BAFFBABA)) 
    \s_axi_rresp[1]_INST_0_i_1 
       (.I0(\s_axi_rresp[1]_INST_0_i_2_n_0 ),
        .I1(\S_AXI_RRESP_ACC_reg[0] ),
        .I2(\USE_READ.rd_cmd_size [2]),
        .I3(\s_axi_rresp[1]_INST_0_i_3_n_0 ),
        .I4(\current_word_1_reg[1] ),
        .I5(\S_AXI_RRESP_ACC_reg[0]_0 ),
        .O(\goreg_dm.dout_i_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT5 #(
    .INIT(32'hFFF0C8C0)) 
    \s_axi_rresp[1]_INST_0_i_2 
       (.I0(\USE_READ.rd_cmd_size [0]),
        .I1(\current_word_1_reg[2] ),
        .I2(\USE_READ.rd_cmd_size [2]),
        .I3(\USE_READ.rd_cmd_size [1]),
        .I4(\current_word_1_reg[1]_0 ),
        .O(\s_axi_rresp[1]_INST_0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \s_axi_rresp[1]_INST_0_i_3 
       (.I0(\USE_READ.rd_cmd_size [1]),
        .I1(\USE_READ.rd_cmd_size [2]),
        .I2(\USE_READ.rd_cmd_size [0]),
        .O(\s_axi_rresp[1]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FEFF0000)) 
    s_axi_rvalid_INST_0
       (.I0(s_axi_rvalid_0),
        .I1(dout[18]),
        .I2(dout[19]),
        .I3(s_axi_rvalid_INST_0_i_2_n_0),
        .I4(m_axi_rvalid),
        .I5(empty),
        .O(s_axi_rvalid));
  LUT6 #(
    .INIT(64'hFFFFFFFFEEC0EE00)) 
    s_axi_rvalid_INST_0_i_2
       (.I0(\goreg_dm.dout_i_reg[17] [3]),
        .I1(\goreg_dm.dout_i_reg[17] [2]),
        .I2(\USE_READ.rd_cmd_size [0]),
        .I3(\USE_READ.rd_cmd_size [2]),
        .I4(\USE_READ.rd_cmd_size [1]),
        .I5(s_axi_rvalid_INST_0_i_4_n_0),
        .O(s_axi_rvalid_INST_0_i_2_n_0));
  LUT5 #(
    .INIT(32'hFFFCA8A8)) 
    s_axi_rvalid_INST_0_i_4
       (.I0(\goreg_dm.dout_i_reg[17] [1]),
        .I1(\USE_READ.rd_cmd_size [1]),
        .I2(\USE_READ.rd_cmd_size [2]),
        .I3(\USE_READ.rd_cmd_size [0]),
        .I4(\goreg_dm.dout_i_reg[17] [0]),
        .O(s_axi_rvalid_INST_0_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT2 #(
    .INIT(4'h8)) 
    split_ongoing_i_1__0
       (.I0(m_axi_arready),
        .I1(command_ongoing_reg),
        .O(m_axi_arready_1));
endmodule

(* ORIG_REF_NAME = "axi_data_fifo_v2_1_28_fifo_gen" *) 
module design_1_auto_ds_0_axi_data_fifo_v2_1_28_fifo_gen__parameterized0__xdcDup__1
   (dout,
    access_fit_mi_side_q_reg,
    E,
    D,
    s_axi_awvalid_0,
    command_ongoing_reg,
    cmd_b_push_block_reg,
    cmd_b_push_block_reg_0,
    cmd_b_push_block_reg_1,
    cmd_push_block_reg,
    m_axi_awready_0,
    wr_en,
    split_ongoing_reg,
    access_is_wrap_q_reg,
    m_axi_wvalid,
    s_axi_wready,
    s_axi_wvalid_0,
    m_axi_wdata,
    m_axi_wstrb,
    \goreg_dm.dout_i_reg[17] ,
    \areset_d_reg[0] ,
    CLK,
    SR,
    din,
    Q,
    fix_need_to_split_q,
    \m_axi_awlen[7]_INST_0_i_6_0 ,
    access_is_wrap_q,
    split_ongoing,
    s_axi_awvalid,
    S_AXI_AREADY_I_reg,
    S_AXI_AREADY_I_reg_0,
    S_AXI_AREADY_I_reg_1,
    command_ongoing,
    m_axi_awready,
    command_ongoing_reg_0,
    cmd_b_push_block,
    out,
    \USE_WRITE.wr_cmd_b_ready ,
    \USE_B_CHANNEL.cmd_b_empty_i_reg ,
    cmd_b_empty,
    cmd_push_block,
    full,
    m_axi_awvalid_INST_0_i_1_0,
    s_axi_bid,
    access_is_fix_q,
    \m_axi_awlen[7] ,
    \m_axi_awlen[7]_0 ,
    \m_axi_awlen[7]_INST_0_i_6_1 ,
    wrap_need_to_split_q,
    \m_axi_awlen[4] ,
    incr_need_to_split_q,
    \m_axi_awlen[7]_INST_0_i_5_0 ,
    access_is_incr_q,
    \m_axi_awlen[7]_INST_0_i_5_1 ,
    \gpr1.dout_i_reg[15] ,
    si_full_size_q,
    \gpr1.dout_i_reg[15]_0 ,
    \gpr1.dout_i_reg[15]_1 ,
    \gpr1.dout_i_reg[15]_2 ,
    \gpr1.dout_i_reg[15]_3 ,
    \m_axi_awlen[4]_INST_0_i_3_0 ,
    legal_wrap_len_q,
    s_axi_wvalid,
    m_axi_wready,
    s_axi_wready_0,
    s_axi_wdata,
    s_axi_wstrb,
    \current_word_1_reg[3] ,
    first_mi_word,
    \current_word_1_reg[2] ,
    m_axi_wstrb_3_sp_1,
    \current_word_1_reg[1] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1_reg[3]_0 );
  output [15:0]dout;
  output [10:0]access_fit_mi_side_q_reg;
  output [0:0]E;
  output [4:0]D;
  output s_axi_awvalid_0;
  output command_ongoing_reg;
  output cmd_b_push_block_reg;
  output [0:0]cmd_b_push_block_reg_0;
  output cmd_b_push_block_reg_1;
  output cmd_push_block_reg;
  output [0:0]m_axi_awready_0;
  output wr_en;
  output split_ongoing_reg;
  output access_is_wrap_q_reg;
  output m_axi_wvalid;
  output s_axi_wready;
  output [0:0]s_axi_wvalid_0;
  output [31:0]m_axi_wdata;
  output [3:0]m_axi_wstrb;
  output [3:0]\goreg_dm.dout_i_reg[17] ;
  output \areset_d_reg[0] ;
  input CLK;
  input [0:0]SR;
  input [8:0]din;
  input [5:0]Q;
  input fix_need_to_split_q;
  input [7:0]\m_axi_awlen[7]_INST_0_i_6_0 ;
  input access_is_wrap_q;
  input split_ongoing;
  input s_axi_awvalid;
  input [0:0]S_AXI_AREADY_I_reg;
  input S_AXI_AREADY_I_reg_0;
  input S_AXI_AREADY_I_reg_1;
  input command_ongoing;
  input m_axi_awready;
  input command_ongoing_reg_0;
  input cmd_b_push_block;
  input out;
  input \USE_WRITE.wr_cmd_b_ready ;
  input \USE_B_CHANNEL.cmd_b_empty_i_reg ;
  input cmd_b_empty;
  input cmd_push_block;
  input full;
  input [15:0]m_axi_awvalid_INST_0_i_1_0;
  input [15:0]s_axi_bid;
  input access_is_fix_q;
  input [7:0]\m_axi_awlen[7] ;
  input [7:0]\m_axi_awlen[7]_0 ;
  input [7:0]\m_axi_awlen[7]_INST_0_i_6_1 ;
  input wrap_need_to_split_q;
  input [4:0]\m_axi_awlen[4] ;
  input incr_need_to_split_q;
  input \m_axi_awlen[7]_INST_0_i_5_0 ;
  input access_is_incr_q;
  input \m_axi_awlen[7]_INST_0_i_5_1 ;
  input \gpr1.dout_i_reg[15] ;
  input si_full_size_q;
  input [1:0]\gpr1.dout_i_reg[15]_0 ;
  input [3:0]\gpr1.dout_i_reg[15]_1 ;
  input \gpr1.dout_i_reg[15]_2 ;
  input \gpr1.dout_i_reg[15]_3 ;
  input [4:0]\m_axi_awlen[4]_INST_0_i_3_0 ;
  input legal_wrap_len_q;
  input s_axi_wvalid;
  input m_axi_wready;
  input s_axi_wready_0;
  input [127:0]s_axi_wdata;
  input [15:0]s_axi_wstrb;
  input [2:0]\current_word_1_reg[3] ;
  input first_mi_word;
  input \current_word_1_reg[2] ;
  input m_axi_wstrb_3_sp_1;
  input \current_word_1_reg[1] ;
  input \current_word_1_reg[1]_0 ;
  input \current_word_1_reg[3]_0 ;

  wire CLK;
  wire [4:0]D;
  wire [0:0]E;
  wire [5:0]Q;
  wire [0:0]SR;
  wire S_AXI_AREADY_I_i_3_n_0;
  wire [0:0]S_AXI_AREADY_I_reg;
  wire S_AXI_AREADY_I_reg_0;
  wire S_AXI_AREADY_I_reg_1;
  wire \USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0 ;
  wire \USE_B_CHANNEL.cmd_b_empty_i_reg ;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire [3:0]\USE_WRITE.wr_cmd_mask ;
  wire \USE_WRITE.wr_cmd_mirror ;
  wire [3:0]\USE_WRITE.wr_cmd_offset ;
  wire \USE_WRITE.wr_cmd_ready ;
  wire [2:0]\USE_WRITE.wr_cmd_size ;
  wire [10:0]access_fit_mi_side_q_reg;
  wire access_is_fix_q;
  wire access_is_incr_q;
  wire access_is_wrap_q;
  wire access_is_wrap_q_reg;
  wire \areset_d_reg[0] ;
  wire cmd_b_empty;
  wire cmd_b_empty0;
  wire cmd_b_push_block;
  wire cmd_b_push_block_reg;
  wire [0:0]cmd_b_push_block_reg_0;
  wire cmd_b_push_block_reg_1;
  wire cmd_push_block;
  wire cmd_push_block_reg;
  wire command_ongoing;
  wire command_ongoing_reg;
  wire command_ongoing_reg_0;
  wire \current_word_1[2]_i_2__0_n_0 ;
  wire \current_word_1_reg[1] ;
  wire \current_word_1_reg[1]_0 ;
  wire \current_word_1_reg[2] ;
  wire [2:0]\current_word_1_reg[3] ;
  wire \current_word_1_reg[3]_0 ;
  wire [8:0]din;
  wire [15:0]dout;
  wire empty;
  wire fifo_gen_inst_i_11_n_0;
  wire fifo_gen_inst_i_12_n_0;
  wire first_mi_word;
  wire fix_need_to_split_q;
  wire full;
  wire full_0;
  wire [3:0]\goreg_dm.dout_i_reg[17] ;
  wire \gpr1.dout_i_reg[15] ;
  wire [1:0]\gpr1.dout_i_reg[15]_0 ;
  wire [3:0]\gpr1.dout_i_reg[15]_1 ;
  wire \gpr1.dout_i_reg[15]_2 ;
  wire \gpr1.dout_i_reg[15]_3 ;
  wire incr_need_to_split_q;
  wire legal_wrap_len_q;
  wire \m_axi_awlen[0]_INST_0_i_1_n_0 ;
  wire \m_axi_awlen[1]_INST_0_i_1_n_0 ;
  wire \m_axi_awlen[1]_INST_0_i_2_n_0 ;
  wire \m_axi_awlen[1]_INST_0_i_3_n_0 ;
  wire \m_axi_awlen[1]_INST_0_i_4_n_0 ;
  wire \m_axi_awlen[1]_INST_0_i_5_n_0 ;
  wire \m_axi_awlen[2]_INST_0_i_1_n_0 ;
  wire \m_axi_awlen[2]_INST_0_i_2_n_0 ;
  wire \m_axi_awlen[2]_INST_0_i_3_n_0 ;
  wire \m_axi_awlen[3]_INST_0_i_1_n_0 ;
  wire \m_axi_awlen[3]_INST_0_i_2_n_0 ;
  wire \m_axi_awlen[3]_INST_0_i_3_n_0 ;
  wire \m_axi_awlen[3]_INST_0_i_4_n_0 ;
  wire \m_axi_awlen[3]_INST_0_i_5_n_0 ;
  wire [4:0]\m_axi_awlen[4] ;
  wire \m_axi_awlen[4]_INST_0_i_1_n_0 ;
  wire \m_axi_awlen[4]_INST_0_i_2_n_0 ;
  wire [4:0]\m_axi_awlen[4]_INST_0_i_3_0 ;
  wire \m_axi_awlen[4]_INST_0_i_3_n_0 ;
  wire \m_axi_awlen[4]_INST_0_i_4_n_0 ;
  wire \m_axi_awlen[6]_INST_0_i_1_n_0 ;
  wire [7:0]\m_axi_awlen[7] ;
  wire [7:0]\m_axi_awlen[7]_0 ;
  wire \m_axi_awlen[7]_INST_0_i_10_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_11_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_12_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_13_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_16_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_1_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_2_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_3_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_4_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_5_0 ;
  wire \m_axi_awlen[7]_INST_0_i_5_1 ;
  wire \m_axi_awlen[7]_INST_0_i_5_n_0 ;
  wire [7:0]\m_axi_awlen[7]_INST_0_i_6_0 ;
  wire [7:0]\m_axi_awlen[7]_INST_0_i_6_1 ;
  wire \m_axi_awlen[7]_INST_0_i_6_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_7_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_8_n_0 ;
  wire \m_axi_awlen[7]_INST_0_i_9_n_0 ;
  wire m_axi_awready;
  wire [0:0]m_axi_awready_0;
  wire [15:0]m_axi_awvalid_INST_0_i_1_0;
  wire m_axi_awvalid_INST_0_i_1_n_0;
  wire m_axi_awvalid_INST_0_i_2_n_0;
  wire m_axi_awvalid_INST_0_i_3_n_0;
  wire m_axi_awvalid_INST_0_i_4_n_0;
  wire m_axi_awvalid_INST_0_i_5_n_0;
  wire m_axi_awvalid_INST_0_i_6_n_0;
  wire m_axi_awvalid_INST_0_i_7_n_0;
  wire [31:0]m_axi_wdata;
  wire \m_axi_wdata[31]_INST_0_i_1_n_0 ;
  wire \m_axi_wdata[31]_INST_0_i_2_n_0 ;
  wire \m_axi_wdata[31]_INST_0_i_3_n_0 ;
  wire \m_axi_wdata[31]_INST_0_i_6_n_0 ;
  wire m_axi_wready;
  wire [3:0]m_axi_wstrb;
  wire m_axi_wstrb_3_sn_1;
  wire m_axi_wvalid;
  wire out;
  wire [28:18]p_0_out;
  wire s_axi_awvalid;
  wire s_axi_awvalid_0;
  wire [15:0]s_axi_bid;
  wire [127:0]s_axi_wdata;
  wire s_axi_wready;
  wire s_axi_wready_0;
  wire s_axi_wready_INST_0_i_1_n_0;
  wire s_axi_wready_INST_0_i_2_n_0;
  wire [15:0]s_axi_wstrb;
  wire s_axi_wvalid;
  wire [0:0]s_axi_wvalid_0;
  wire si_full_size_q;
  wire split_ongoing;
  wire split_ongoing_reg;
  wire wr_en;
  wire wrap_need_to_split_q;
  wire NLW_fifo_gen_inst_almost_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_almost_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_axis_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_dbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_overflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_prog_empty_UNCONNECTED;
  wire NLW_fifo_gen_inst_prog_full_UNCONNECTED;
  wire NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED;
  wire NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED;
  wire NLW_fifo_gen_inst_sbiterr_UNCONNECTED;
  wire NLW_fifo_gen_inst_underflow_UNCONNECTED;
  wire NLW_fifo_gen_inst_valid_UNCONNECTED;
  wire NLW_fifo_gen_inst_wr_ack_UNCONNECTED;
  wire NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED;
  wire [4:0]NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED;
  wire [10:0]NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_data_count_UNCONNECTED;
  wire [27:27]NLW_fifo_gen_inst_dout_UNCONNECTED;
  wire [31:0]NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED;
  wire [31:0]NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED;
  wire [2:0]NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED;
  wire [7:0]NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_rd_data_count_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED;
  wire [63:0]NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED;
  wire [3:0]NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED;
  wire [0:0]NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED;
  wire [5:0]NLW_fifo_gen_inst_wr_data_count_UNCONNECTED;

  assign m_axi_wstrb_3_sn_1 = m_axi_wstrb_3_sp_1;
  LUT5 #(
    .INIT(32'h44F4FFF4)) 
    S_AXI_AREADY_I_i_2
       (.I0(S_AXI_AREADY_I_reg_0),
        .I1(S_AXI_AREADY_I_reg_1),
        .I2(S_AXI_AREADY_I_i_3_n_0),
        .I3(S_AXI_AREADY_I_reg),
        .I4(s_axi_awvalid),
        .O(\areset_d_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT3 #(
    .INIT(8'h08)) 
    S_AXI_AREADY_I_i_3
       (.I0(m_axi_awready),
        .I1(command_ongoing_reg),
        .I2(command_ongoing_reg_0),
        .O(S_AXI_AREADY_I_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT3 #(
    .INIT(8'h69)) 
    \USE_B_CHANNEL.cmd_b_depth[1]_i_1 
       (.I0(Q[0]),
        .I1(cmd_b_empty0),
        .I2(Q[1]),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT4 #(
    .INIT(16'h78E1)) 
    \USE_B_CHANNEL.cmd_b_depth[2]_i_1 
       (.I0(cmd_b_empty0),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[1]),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT5 #(
    .INIT(32'h7FFE8001)) 
    \USE_B_CHANNEL.cmd_b_depth[3]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(cmd_b_empty0),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAA9)) 
    \USE_B_CHANNEL.cmd_b_depth[4]_i_1 
       (.I0(Q[4]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(cmd_b_empty0),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \USE_B_CHANNEL.cmd_b_depth[4]_i_2 
       (.I0(command_ongoing_reg),
        .I1(cmd_b_push_block),
        .I2(\USE_WRITE.wr_cmd_b_ready ),
        .O(cmd_b_empty0));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \USE_B_CHANNEL.cmd_b_depth[5]_i_1 
       (.I0(command_ongoing_reg),
        .I1(cmd_b_push_block),
        .I2(\USE_WRITE.wr_cmd_b_ready ),
        .O(cmd_b_push_block_reg_0));
  LUT5 #(
    .INIT(32'h6AAAAAA9)) 
    \USE_B_CHANNEL.cmd_b_depth[5]_i_2 
       (.I0(Q[5]),
        .I1(Q[4]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0 ),
        .O(D[4]));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT4 #(
    .INIT(16'h80FE)) 
    \USE_B_CHANNEL.cmd_b_depth[5]_i_3 
       (.I0(cmd_b_empty0),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .O(\USE_B_CHANNEL.cmd_b_depth[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT5 #(
    .INIT(32'hF2DDD000)) 
    \USE_B_CHANNEL.cmd_b_empty_i_i_1 
       (.I0(command_ongoing_reg),
        .I1(cmd_b_push_block),
        .I2(\USE_B_CHANNEL.cmd_b_empty_i_reg ),
        .I3(\USE_WRITE.wr_cmd_b_ready ),
        .I4(cmd_b_empty),
        .O(cmd_b_push_block_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT4 #(
    .INIT(16'h00E0)) 
    cmd_b_push_block_i_1
       (.I0(command_ongoing_reg),
        .I1(cmd_b_push_block),
        .I2(out),
        .I3(S_AXI_AREADY_I_reg),
        .O(cmd_b_push_block_reg));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT4 #(
    .INIT(16'h4E00)) 
    cmd_push_block_i_1
       (.I0(command_ongoing_reg),
        .I1(cmd_push_block),
        .I2(m_axi_awready),
        .I3(out),
        .O(cmd_push_block_reg));
  LUT6 #(
    .INIT(64'h8FFF8F8F88008888)) 
    command_ongoing_i_1
       (.I0(s_axi_awvalid),
        .I1(S_AXI_AREADY_I_reg),
        .I2(S_AXI_AREADY_I_i_3_n_0),
        .I3(S_AXI_AREADY_I_reg_0),
        .I4(S_AXI_AREADY_I_reg_1),
        .I5(command_ongoing),
        .O(s_axi_awvalid_0));
  LUT5 #(
    .INIT(32'h22222228)) 
    \current_word_1[0]_i_1__0 
       (.I0(\USE_WRITE.wr_cmd_mask [0]),
        .I1(\current_word_1_reg[1]_0 ),
        .I2(dout[9]),
        .I3(dout[10]),
        .I4(dout[8]),
        .O(\goreg_dm.dout_i_reg[17] [0]));
  LUT6 #(
    .INIT(64'h8888828888888282)) 
    \current_word_1[1]_i_1__0 
       (.I0(\USE_WRITE.wr_cmd_mask [1]),
        .I1(\current_word_1_reg[1] ),
        .I2(dout[10]),
        .I3(dout[8]),
        .I4(dout[9]),
        .I5(\current_word_1_reg[1]_0 ),
        .O(\goreg_dm.dout_i_reg[17] [1]));
  LUT6 #(
    .INIT(64'h2228222288828888)) 
    \current_word_1[2]_i_1__0 
       (.I0(\USE_WRITE.wr_cmd_mask [2]),
        .I1(\current_word_1_reg[2] ),
        .I2(dout[8]),
        .I3(dout[10]),
        .I4(dout[9]),
        .I5(\current_word_1[2]_i_2__0_n_0 ),
        .O(\goreg_dm.dout_i_reg[17] [2]));
  LUT5 #(
    .INIT(32'h0008000A)) 
    \current_word_1[2]_i_2__0 
       (.I0(\current_word_1_reg[1] ),
        .I1(dout[8]),
        .I2(dout[10]),
        .I3(dout[9]),
        .I4(\current_word_1_reg[1]_0 ),
        .O(\current_word_1[2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0002AAA2AAA80008)) 
    \current_word_1[3]_i_1__0 
       (.I0(\USE_WRITE.wr_cmd_mask [3]),
        .I1(\current_word_1_reg[3] [2]),
        .I2(dout[15]),
        .I3(first_mi_word),
        .I4(dout[14]),
        .I5(\current_word_1_reg[3]_0 ),
        .O(\goreg_dm.dout_i_reg[17] [3]));
  (* C_ADD_NGC_CONSTRAINT = "0" *) 
  (* C_APPLICATION_TYPE_AXIS = "0" *) 
  (* C_APPLICATION_TYPE_RACH = "0" *) 
  (* C_APPLICATION_TYPE_RDCH = "0" *) 
  (* C_APPLICATION_TYPE_WACH = "0" *) 
  (* C_APPLICATION_TYPE_WDCH = "0" *) 
  (* C_APPLICATION_TYPE_WRCH = "0" *) 
  (* C_AXIS_TDATA_WIDTH = "64" *) 
  (* C_AXIS_TDEST_WIDTH = "4" *) 
  (* C_AXIS_TID_WIDTH = "8" *) 
  (* C_AXIS_TKEEP_WIDTH = "4" *) 
  (* C_AXIS_TSTRB_WIDTH = "4" *) 
  (* C_AXIS_TUSER_WIDTH = "4" *) 
  (* C_AXIS_TYPE = "0" *) 
  (* C_AXI_ADDR_WIDTH = "32" *) 
  (* C_AXI_ARUSER_WIDTH = "1" *) 
  (* C_AXI_AWUSER_WIDTH = "1" *) 
  (* C_AXI_BUSER_WIDTH = "1" *) 
  (* C_AXI_DATA_WIDTH = "64" *) 
  (* C_AXI_ID_WIDTH = "4" *) 
  (* C_AXI_LEN_WIDTH = "8" *) 
  (* C_AXI_LOCK_WIDTH = "2" *) 
  (* C_AXI_RUSER_WIDTH = "1" *) 
  (* C_AXI_TYPE = "0" *) 
  (* C_AXI_WUSER_WIDTH = "1" *) 
  (* C_COMMON_CLOCK = "1" *) 
  (* C_COUNT_TYPE = "0" *) 
  (* C_DATA_COUNT_WIDTH = "6" *) 
  (* C_DEFAULT_VALUE = "BlankString" *) 
  (* C_DIN_WIDTH = "29" *) 
  (* C_DIN_WIDTH_AXIS = "1" *) 
  (* C_DIN_WIDTH_RACH = "32" *) 
  (* C_DIN_WIDTH_RDCH = "64" *) 
  (* C_DIN_WIDTH_WACH = "32" *) 
  (* C_DIN_WIDTH_WDCH = "64" *) 
  (* C_DIN_WIDTH_WRCH = "2" *) 
  (* C_DOUT_RST_VAL = "0" *) 
  (* C_DOUT_WIDTH = "29" *) 
  (* C_ENABLE_RLOCS = "0" *) 
  (* C_ENABLE_RST_SYNC = "1" *) 
  (* C_EN_SAFETY_CKT = "0" *) 
  (* C_ERROR_INJECTION_TYPE = "0" *) 
  (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WACH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) 
  (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) 
  (* C_FAMILY = "zynquplus" *) 
  (* C_FULL_FLAGS_RST_VAL = "0" *) 
  (* C_HAS_ALMOST_EMPTY = "0" *) 
  (* C_HAS_ALMOST_FULL = "0" *) 
  (* C_HAS_AXIS_TDATA = "0" *) 
  (* C_HAS_AXIS_TDEST = "0" *) 
  (* C_HAS_AXIS_TID = "0" *) 
  (* C_HAS_AXIS_TKEEP = "0" *) 
  (* C_HAS_AXIS_TLAST = "0" *) 
  (* C_HAS_AXIS_TREADY = "1" *) 
  (* C_HAS_AXIS_TSTRB = "0" *) 
  (* C_HAS_AXIS_TUSER = "0" *) 
  (* C_HAS_AXI_ARUSER = "0" *) 
  (* C_HAS_AXI_AWUSER = "0" *) 
  (* C_HAS_AXI_BUSER = "0" *) 
  (* C_HAS_AXI_ID = "0" *) 
  (* C_HAS_AXI_RD_CHANNEL = "0" *) 
  (* C_HAS_AXI_RUSER = "0" *) 
  (* C_HAS_AXI_WR_CHANNEL = "0" *) 
  (* C_HAS_AXI_WUSER = "0" *) 
  (* C_HAS_BACKUP = "0" *) 
  (* C_HAS_DATA_COUNT = "0" *) 
  (* C_HAS_DATA_COUNTS_AXIS = "0" *) 
  (* C_HAS_DATA_COUNTS_RACH = "0" *) 
  (* C_HAS_DATA_COUNTS_RDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WACH = "0" *) 
  (* C_HAS_DATA_COUNTS_WDCH = "0" *) 
  (* C_HAS_DATA_COUNTS_WRCH = "0" *) 
  (* C_HAS_INT_CLK = "0" *) 
  (* C_HAS_MASTER_CE = "0" *) 
  (* C_HAS_MEMINIT_FILE = "0" *) 
  (* C_HAS_OVERFLOW = "0" *) 
  (* C_HAS_PROG_FLAGS_AXIS = "0" *) 
  (* C_HAS_PROG_FLAGS_RACH = "0" *) 
  (* C_HAS_PROG_FLAGS_RDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WACH = "0" *) 
  (* C_HAS_PROG_FLAGS_WDCH = "0" *) 
  (* C_HAS_PROG_FLAGS_WRCH = "0" *) 
  (* C_HAS_RD_DATA_COUNT = "0" *) 
  (* C_HAS_RD_RST = "0" *) 
  (* C_HAS_RST = "1" *) 
  (* C_HAS_SLAVE_CE = "0" *) 
  (* C_HAS_SRST = "0" *) 
  (* C_HAS_UNDERFLOW = "0" *) 
  (* C_HAS_VALID = "0" *) 
  (* C_HAS_WR_ACK = "0" *) 
  (* C_HAS_WR_DATA_COUNT = "0" *) 
  (* C_HAS_WR_RST = "0" *) 
  (* C_IMPLEMENTATION_TYPE = "0" *) 
  (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RACH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WACH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) 
  (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) 
  (* C_INIT_WR_PNTR_VAL = "0" *) 
  (* C_INTERFACE_TYPE = "0" *) 
  (* C_MEMORY_TYPE = "2" *) 
  (* C_MIF_FILE_NAME = "BlankString" *) 
  (* C_MSGON_VAL = "1" *) 
  (* C_OPTIMIZATION_MODE = "0" *) 
  (* C_OVERFLOW_LOW = "0" *) 
  (* C_POWER_SAVING_MODE = "0" *) 
  (* C_PRELOAD_LATENCY = "0" *) 
  (* C_PRELOAD_REGS = "1" *) 
  (* C_PRIM_FIFO_TYPE = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) 
  (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) 
  (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) 
  (* C_PROG_EMPTY_TYPE = "0" *) 
  (* C_PROG_EMPTY_TYPE_AXIS = "0" *) 
  (* C_PROG_EMPTY_TYPE_RACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_RDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WACH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WDCH = "0" *) 
  (* C_PROG_EMPTY_TYPE_WRCH = "0" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL = "31" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) 
  (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) 
  (* C_PROG_FULL_THRESH_NEGATE_VAL = "30" *) 
  (* C_PROG_FULL_TYPE = "0" *) 
  (* C_PROG_FULL_TYPE_AXIS = "0" *) 
  (* C_PROG_FULL_TYPE_RACH = "0" *) 
  (* C_PROG_FULL_TYPE_RDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WACH = "0" *) 
  (* C_PROG_FULL_TYPE_WDCH = "0" *) 
  (* C_PROG_FULL_TYPE_WRCH = "0" *) 
  (* C_RACH_TYPE = "0" *) 
  (* C_RDCH_TYPE = "0" *) 
  (* C_RD_DATA_COUNT_WIDTH = "6" *) 
  (* C_RD_DEPTH = "32" *) 
  (* C_RD_FREQ = "1" *) 
  (* C_RD_PNTR_WIDTH = "5" *) 
  (* C_REG_SLICE_MODE_AXIS = "0" *) 
  (* C_REG_SLICE_MODE_RACH = "0" *) 
  (* C_REG_SLICE_MODE_RDCH = "0" *) 
  (* C_REG_SLICE_MODE_WACH = "0" *) 
  (* C_REG_SLICE_MODE_WDCH = "0" *) 
  (* C_REG_SLICE_MODE_WRCH = "0" *) 
  (* C_SELECT_XPM = "0" *) 
  (* C_SYNCHRONIZER_STAGE = "3" *) 
  (* C_UNDERFLOW_LOW = "0" *) 
  (* C_USE_COMMON_OVERFLOW = "0" *) 
  (* C_USE_COMMON_UNDERFLOW = "0" *) 
  (* C_USE_DEFAULT_SETTINGS = "0" *) 
  (* C_USE_DOUT_RST = "0" *) 
  (* C_USE_ECC = "0" *) 
  (* C_USE_ECC_AXIS = "0" *) 
  (* C_USE_ECC_RACH = "0" *) 
  (* C_USE_ECC_RDCH = "0" *) 
  (* C_USE_ECC_WACH = "0" *) 
  (* C_USE_ECC_WDCH = "0" *) 
  (* C_USE_ECC_WRCH = "0" *) 
  (* C_USE_EMBEDDED_REG = "0" *) 
  (* C_USE_FIFO16_FLAGS = "0" *) 
  (* C_USE_FWFT_DATA_COUNT = "1" *) 
  (* C_USE_PIPELINE_REG = "0" *) 
  (* C_VALID_LOW = "0" *) 
  (* C_WACH_TYPE = "0" *) 
  (* C_WDCH_TYPE = "0" *) 
  (* C_WRCH_TYPE = "0" *) 
  (* C_WR_ACK_LOW = "0" *) 
  (* C_WR_DATA_COUNT_WIDTH = "6" *) 
  (* C_WR_DEPTH = "32" *) 
  (* C_WR_DEPTH_AXIS = "1024" *) 
  (* C_WR_DEPTH_RACH = "16" *) 
  (* C_WR_DEPTH_RDCH = "1024" *) 
  (* C_WR_DEPTH_WACH = "16" *) 
  (* C_WR_DEPTH_WDCH = "1024" *) 
  (* C_WR_DEPTH_WRCH = "16" *) 
  (* C_WR_FREQ = "1" *) 
  (* C_WR_PNTR_WIDTH = "5" *) 
  (* C_WR_PNTR_WIDTH_AXIS = "10" *) 
  (* C_WR_PNTR_WIDTH_RACH = "4" *) 
  (* C_WR_PNTR_WIDTH_RDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WACH = "4" *) 
  (* C_WR_PNTR_WIDTH_WDCH = "10" *) 
  (* C_WR_PNTR_WIDTH_WRCH = "4" *) 
  (* C_WR_RESPONSE_LATENCY = "1" *) 
  (* KEEP_HIERARCHY = "soft" *) 
  (* is_du_within_envelope = "true" *) 
  design_1_auto_ds_0_fifo_generator_v13_2_9__parameterized0__xdcDup__1 fifo_gen_inst
       (.almost_empty(NLW_fifo_gen_inst_almost_empty_UNCONNECTED),
        .almost_full(NLW_fifo_gen_inst_almost_full_UNCONNECTED),
        .axi_ar_data_count(NLW_fifo_gen_inst_axi_ar_data_count_UNCONNECTED[4:0]),
        .axi_ar_dbiterr(NLW_fifo_gen_inst_axi_ar_dbiterr_UNCONNECTED),
        .axi_ar_injectdbiterr(1'b0),
        .axi_ar_injectsbiterr(1'b0),
        .axi_ar_overflow(NLW_fifo_gen_inst_axi_ar_overflow_UNCONNECTED),
        .axi_ar_prog_empty(NLW_fifo_gen_inst_axi_ar_prog_empty_UNCONNECTED),
        .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_prog_full(NLW_fifo_gen_inst_axi_ar_prog_full_UNCONNECTED),
        .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_ar_rd_data_count(NLW_fifo_gen_inst_axi_ar_rd_data_count_UNCONNECTED[4:0]),
        .axi_ar_sbiterr(NLW_fifo_gen_inst_axi_ar_sbiterr_UNCONNECTED),
        .axi_ar_underflow(NLW_fifo_gen_inst_axi_ar_underflow_UNCONNECTED),
        .axi_ar_wr_data_count(NLW_fifo_gen_inst_axi_ar_wr_data_count_UNCONNECTED[4:0]),
        .axi_aw_data_count(NLW_fifo_gen_inst_axi_aw_data_count_UNCONNECTED[4:0]),
        .axi_aw_dbiterr(NLW_fifo_gen_inst_axi_aw_dbiterr_UNCONNECTED),
        .axi_aw_injectdbiterr(1'b0),
        .axi_aw_injectsbiterr(1'b0),
        .axi_aw_overflow(NLW_fifo_gen_inst_axi_aw_overflow_UNCONNECTED),
        .axi_aw_prog_empty(NLW_fifo_gen_inst_axi_aw_prog_empty_UNCONNECTED),
        .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_prog_full(NLW_fifo_gen_inst_axi_aw_prog_full_UNCONNECTED),
        .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_aw_rd_data_count(NLW_fifo_gen_inst_axi_aw_rd_data_count_UNCONNECTED[4:0]),
        .axi_aw_sbiterr(NLW_fifo_gen_inst_axi_aw_sbiterr_UNCONNECTED),
        .axi_aw_underflow(NLW_fifo_gen_inst_axi_aw_underflow_UNCONNECTED),
        .axi_aw_wr_data_count(NLW_fifo_gen_inst_axi_aw_wr_data_count_UNCONNECTED[4:0]),
        .axi_b_data_count(NLW_fifo_gen_inst_axi_b_data_count_UNCONNECTED[4:0]),
        .axi_b_dbiterr(NLW_fifo_gen_inst_axi_b_dbiterr_UNCONNECTED),
        .axi_b_injectdbiterr(1'b0),
        .axi_b_injectsbiterr(1'b0),
        .axi_b_overflow(NLW_fifo_gen_inst_axi_b_overflow_UNCONNECTED),
        .axi_b_prog_empty(NLW_fifo_gen_inst_axi_b_prog_empty_UNCONNECTED),
        .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_prog_full(NLW_fifo_gen_inst_axi_b_prog_full_UNCONNECTED),
        .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
        .axi_b_rd_data_count(NLW_fifo_gen_inst_axi_b_rd_data_count_UNCONNECTED[4:0]),
        .axi_b_sbiterr(NLW_fifo_gen_inst_axi_b_sbiterr_UNCONNECTED),
        .axi_b_underflow(NLW_fifo_gen_inst_axi_b_underflow_UNCONNECTED),
        .axi_b_wr_data_count(NLW_fifo_gen_inst_axi_b_wr_data_count_UNCONNECTED[4:0]),
        .axi_r_data_count(NLW_fifo_gen_inst_axi_r_data_count_UNCONNECTED[10:0]),
        .axi_r_dbiterr(NLW_fifo_gen_inst_axi_r_dbiterr_UNCONNECTED),
        .axi_r_injectdbiterr(1'b0),
        .axi_r_injectsbiterr(1'b0),
        .axi_r_overflow(NLW_fifo_gen_inst_axi_r_overflow_UNCONNECTED),
        .axi_r_prog_empty(NLW_fifo_gen_inst_axi_r_prog_empty_UNCONNECTED),
        .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_prog_full(NLW_fifo_gen_inst_axi_r_prog_full_UNCONNECTED),
        .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_r_rd_data_count(NLW_fifo_gen_inst_axi_r_rd_data_count_UNCONNECTED[10:0]),
        .axi_r_sbiterr(NLW_fifo_gen_inst_axi_r_sbiterr_UNCONNECTED),
        .axi_r_underflow(NLW_fifo_gen_inst_axi_r_underflow_UNCONNECTED),
        .axi_r_wr_data_count(NLW_fifo_gen_inst_axi_r_wr_data_count_UNCONNECTED[10:0]),
        .axi_w_data_count(NLW_fifo_gen_inst_axi_w_data_count_UNCONNECTED[10:0]),
        .axi_w_dbiterr(NLW_fifo_gen_inst_axi_w_dbiterr_UNCONNECTED),
        .axi_w_injectdbiterr(1'b0),
        .axi_w_injectsbiterr(1'b0),
        .axi_w_overflow(NLW_fifo_gen_inst_axi_w_overflow_UNCONNECTED),
        .axi_w_prog_empty(NLW_fifo_gen_inst_axi_w_prog_empty_UNCONNECTED),
        .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_prog_full(NLW_fifo_gen_inst_axi_w_prog_full_UNCONNECTED),
        .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axi_w_rd_data_count(NLW_fifo_gen_inst_axi_w_rd_data_count_UNCONNECTED[10:0]),
        .axi_w_sbiterr(NLW_fifo_gen_inst_axi_w_sbiterr_UNCONNECTED),
        .axi_w_underflow(NLW_fifo_gen_inst_axi_w_underflow_UNCONNECTED),
        .axi_w_wr_data_count(NLW_fifo_gen_inst_axi_w_wr_data_count_UNCONNECTED[10:0]),
        .axis_data_count(NLW_fifo_gen_inst_axis_data_count_UNCONNECTED[10:0]),
        .axis_dbiterr(NLW_fifo_gen_inst_axis_dbiterr_UNCONNECTED),
        .axis_injectdbiterr(1'b0),
        .axis_injectsbiterr(1'b0),
        .axis_overflow(NLW_fifo_gen_inst_axis_overflow_UNCONNECTED),
        .axis_prog_empty(NLW_fifo_gen_inst_axis_prog_empty_UNCONNECTED),
        .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_prog_full(NLW_fifo_gen_inst_axis_prog_full_UNCONNECTED),
        .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .axis_rd_data_count(NLW_fifo_gen_inst_axis_rd_data_count_UNCONNECTED[10:0]),
        .axis_sbiterr(NLW_fifo_gen_inst_axis_sbiterr_UNCONNECTED),
        .axis_underflow(NLW_fifo_gen_inst_axis_underflow_UNCONNECTED),
        .axis_wr_data_count(NLW_fifo_gen_inst_axis_wr_data_count_UNCONNECTED[10:0]),
        .backup(1'b0),
        .backup_marker(1'b0),
        .clk(CLK),
        .data_count(NLW_fifo_gen_inst_data_count_UNCONNECTED[5:0]),
        .dbiterr(NLW_fifo_gen_inst_dbiterr_UNCONNECTED),
        .din({p_0_out[28],din[8:7],p_0_out[25:18],din[6:3],access_fit_mi_side_q_reg,din[2:0]}),
        .dout({dout[15],NLW_fifo_gen_inst_dout_UNCONNECTED[27],\USE_WRITE.wr_cmd_mirror ,dout[14:11],\USE_WRITE.wr_cmd_offset ,\USE_WRITE.wr_cmd_mask ,dout[10:0],\USE_WRITE.wr_cmd_size }),
        .empty(empty),
        .full(full_0),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .int_clk(1'b0),
        .m_aclk(1'b0),
        .m_aclk_en(1'b0),
        .m_axi_araddr(NLW_fifo_gen_inst_m_axi_araddr_UNCONNECTED[31:0]),
        .m_axi_arburst(NLW_fifo_gen_inst_m_axi_arburst_UNCONNECTED[1:0]),
        .m_axi_arcache(NLW_fifo_gen_inst_m_axi_arcache_UNCONNECTED[3:0]),
        .m_axi_arid(NLW_fifo_gen_inst_m_axi_arid_UNCONNECTED[3:0]),
        .m_axi_arlen(NLW_fifo_gen_inst_m_axi_arlen_UNCONNECTED[7:0]),
        .m_axi_arlock(NLW_fifo_gen_inst_m_axi_arlock_UNCONNECTED[1:0]),
        .m_axi_arprot(NLW_fifo_gen_inst_m_axi_arprot_UNCONNECTED[2:0]),
        .m_axi_arqos(NLW_fifo_gen_inst_m_axi_arqos_UNCONNECTED[3:0]),
        .m_axi_arready(1'b0),
        .m_axi_arregion(NLW_fifo_gen_inst_m_axi_arregion_UNCONNECTED[3:0]),
        .m_axi_arsize(NLW_fifo_gen_inst_m_axi_arsize_UNCONNECTED[2:0]),
        .m_axi_aruser(NLW_fifo_gen_inst_m_axi_aruser_UNCONNECTED[0]),
        .m_axi_arvalid(NLW_fifo_gen_inst_m_axi_arvalid_UNCONNECTED),
        .m_axi_awaddr(NLW_fifo_gen_inst_m_axi_awaddr_UNCONNECTED[31:0]),
        .m_axi_awburst(NLW_fifo_gen_inst_m_axi_awburst_UNCONNECTED[1:0]),
        .m_axi_awcache(NLW_fifo_gen_inst_m_axi_awcache_UNCONNECTED[3:0]),
        .m_axi_awid(NLW_fifo_gen_inst_m_axi_awid_UNCONNECTED[3:0]),
        .m_axi_awlen(NLW_fifo_gen_inst_m_axi_awlen_UNCONNECTED[7:0]),
        .m_axi_awlock(NLW_fifo_gen_inst_m_axi_awlock_UNCONNECTED[1:0]),
        .m_axi_awprot(NLW_fifo_gen_inst_m_axi_awprot_UNCONNECTED[2:0]),
        .m_axi_awqos(NLW_fifo_gen_inst_m_axi_awqos_UNCONNECTED[3:0]),
        .m_axi_awready(1'b0),
        .m_axi_awregion(NLW_fifo_gen_inst_m_axi_awregion_UNCONNECTED[3:0]),
        .m_axi_awsize(NLW_fifo_gen_inst_m_axi_awsize_UNCONNECTED[2:0]),
        .m_axi_awuser(NLW_fifo_gen_inst_m_axi_awuser_UNCONNECTED[0]),
        .m_axi_awvalid(NLW_fifo_gen_inst_m_axi_awvalid_UNCONNECTED),
        .m_axi_bid({1'b0,1'b0,1'b0,1'b0}),
        .m_axi_bready(NLW_fifo_gen_inst_m_axi_bready_UNCONNECTED),
        .m_axi_bresp({1'b0,1'b0}),
        .m_axi_buser(1'b0),
        .m_axi_bvalid(1'b0),
        .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rid({1'b0,1'b0,1'b0,1'b0}),
        .m_axi_rlast(1'b0),
        .m_axi_rready(NLW_fifo_gen_inst_m_axi_rready_UNCONNECTED),
        .m_axi_rresp({1'b0,1'b0}),
        .m_axi_ruser(1'b0),
        .m_axi_rvalid(1'b0),
        .m_axi_wdata(NLW_fifo_gen_inst_m_axi_wdata_UNCONNECTED[63:0]),
        .m_axi_wid(NLW_fifo_gen_inst_m_axi_wid_UNCONNECTED[3:0]),
        .m_axi_wlast(NLW_fifo_gen_inst_m_axi_wlast_UNCONNECTED),
        .m_axi_wready(1'b0),
        .m_axi_wstrb(NLW_fifo_gen_inst_m_axi_wstrb_UNCONNECTED[7:0]),
        .m_axi_wuser(NLW_fifo_gen_inst_m_axi_wuser_UNCONNECTED[0]),
        .m_axi_wvalid(NLW_fifo_gen_inst_m_axi_wvalid_UNCONNECTED),
        .m_axis_tdata(NLW_fifo_gen_inst_m_axis_tdata_UNCONNECTED[63:0]),
        .m_axis_tdest(NLW_fifo_gen_inst_m_axis_tdest_UNCONNECTED[3:0]),
        .m_axis_tid(NLW_fifo_gen_inst_m_axis_tid_UNCONNECTED[7:0]),
        .m_axis_tkeep(NLW_fifo_gen_inst_m_axis_tkeep_UNCONNECTED[3:0]),
        .m_axis_tlast(NLW_fifo_gen_inst_m_axis_tlast_UNCONNECTED),
        .m_axis_tready(1'b0),
        .m_axis_tstrb(NLW_fifo_gen_inst_m_axis_tstrb_UNCONNECTED[3:0]),
        .m_axis_tuser(NLW_fifo_gen_inst_m_axis_tuser_UNCONNECTED[3:0]),
        .m_axis_tvalid(NLW_fifo_gen_inst_m_axis_tvalid_UNCONNECTED),
        .overflow(NLW_fifo_gen_inst_overflow_UNCONNECTED),
        .prog_empty(NLW_fifo_gen_inst_prog_empty_UNCONNECTED),
        .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full(NLW_fifo_gen_inst_prog_full_UNCONNECTED),
        .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .rd_clk(1'b0),
        .rd_data_count(NLW_fifo_gen_inst_rd_data_count_UNCONNECTED[5:0]),
        .rd_en(\USE_WRITE.wr_cmd_ready ),
        .rd_rst(1'b0),
        .rd_rst_busy(NLW_fifo_gen_inst_rd_rst_busy_UNCONNECTED),
        .rst(SR),
        .s_aclk(1'b0),
        .s_aclk_en(1'b0),
        .s_aresetn(1'b0),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlock({1'b0,1'b0}),
        .s_axi_arprot({1'b0,1'b0,1'b0}),
        .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_fifo_gen_inst_s_axi_arready_UNCONNECTED),
        .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_aruser(1'b0),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlock({1'b0,1'b0}),
        .s_axi_awprot({1'b0,1'b0,1'b0}),
        .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_fifo_gen_inst_s_axi_awready_UNCONNECTED),
        .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awuser(1'b0),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_fifo_gen_inst_s_axi_bid_UNCONNECTED[3:0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_fifo_gen_inst_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_buser(NLW_fifo_gen_inst_s_axi_buser_UNCONNECTED[0]),
        .s_axi_bvalid(NLW_fifo_gen_inst_s_axi_bvalid_UNCONNECTED),
        .s_axi_rdata(NLW_fifo_gen_inst_s_axi_rdata_UNCONNECTED[63:0]),
        .s_axi_rid(NLW_fifo_gen_inst_s_axi_rid_UNCONNECTED[3:0]),
        .s_axi_rlast(NLW_fifo_gen_inst_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_fifo_gen_inst_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_ruser(NLW_fifo_gen_inst_s_axi_ruser_UNCONNECTED[0]),
        .s_axi_rvalid(NLW_fifo_gen_inst_s_axi_rvalid_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_fifo_gen_inst_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wuser(1'b0),
        .s_axi_wvalid(1'b0),
        .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tdest({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tkeep({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tlast(1'b0),
        .s_axis_tready(NLW_fifo_gen_inst_s_axis_tready_UNCONNECTED),
        .s_axis_tstrb({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
        .s_axis_tvalid(1'b0),
        .sbiterr(NLW_fifo_gen_inst_sbiterr_UNCONNECTED),
        .sleep(1'b0),
        .srst(1'b0),
        .underflow(NLW_fifo_gen_inst_underflow_UNCONNECTED),
        .valid(NLW_fifo_gen_inst_valid_UNCONNECTED),
        .wr_ack(NLW_fifo_gen_inst_wr_ack_UNCONNECTED),
        .wr_clk(1'b0),
        .wr_data_count(NLW_fifo_gen_inst_wr_data_count_UNCONNECTED[5:0]),
        .wr_en(E),
        .wr_rst(1'b0),
        .wr_rst_busy(NLW_fifo_gen_inst_wr_rst_busy_UNCONNECTED));
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_1
       (.I0(access_is_fix_q),
        .I1(din[7]),
        .O(p_0_out[28]));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    fifo_gen_inst_i_10
       (.I0(m_axi_wready),
        .I1(empty),
        .I2(s_axi_wvalid),
        .I3(s_axi_wready_0),
        .O(\USE_WRITE.wr_cmd_ready ));
  LUT6 #(
    .INIT(64'h0040CCCC4444CCCC)) 
    fifo_gen_inst_i_11
       (.I0(access_is_wrap_q),
        .I1(\gpr1.dout_i_reg[15]_1 [3]),
        .I2(\gpr1.dout_i_reg[15]_0 [1]),
        .I3(si_full_size_q),
        .I4(split_ongoing),
        .I5(access_is_incr_q),
        .O(fifo_gen_inst_i_11_n_0));
  LUT6 #(
    .INIT(64'h0040CCCC4444CCCC)) 
    fifo_gen_inst_i_12
       (.I0(access_is_wrap_q),
        .I1(\gpr1.dout_i_reg[15]_1 [2]),
        .I2(\gpr1.dout_i_reg[15]_0 [0]),
        .I3(si_full_size_q),
        .I4(split_ongoing),
        .I5(access_is_incr_q),
        .O(fifo_gen_inst_i_12_n_0));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_13
       (.I0(split_ongoing),
        .I1(access_is_incr_q),
        .O(split_ongoing_reg));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT2 #(
    .INIT(4'h8)) 
    fifo_gen_inst_i_14
       (.I0(access_is_wrap_q),
        .I1(split_ongoing),
        .O(access_is_wrap_q_reg));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'h80)) 
    fifo_gen_inst_i_2
       (.I0(fifo_gen_inst_i_11_n_0),
        .I1(din[6]),
        .I2(\gpr1.dout_i_reg[15] ),
        .O(p_0_out[25]));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'h80)) 
    fifo_gen_inst_i_3
       (.I0(fifo_gen_inst_i_12_n_0),
        .I1(din[5]),
        .I2(\gpr1.dout_i_reg[15] ),
        .O(p_0_out[24]));
  LUT6 #(
    .INIT(64'h0070000000000000)) 
    fifo_gen_inst_i_4
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_1 [1]),
        .I3(access_is_wrap_q_reg),
        .I4(din[4]),
        .I5(\gpr1.dout_i_reg[15]_3 ),
        .O(p_0_out[23]));
  LUT6 #(
    .INIT(64'h0070000000000000)) 
    fifo_gen_inst_i_5
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_1 [0]),
        .I3(access_is_wrap_q_reg),
        .I4(din[3]),
        .I5(\gpr1.dout_i_reg[15]_2 ),
        .O(p_0_out[22]));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT2 #(
    .INIT(4'h2)) 
    fifo_gen_inst_i_6
       (.I0(command_ongoing_reg),
        .I1(cmd_b_push_block),
        .O(wr_en));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_6__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_0 [1]),
        .I3(\gpr1.dout_i_reg[15]_1 [3]),
        .I4(access_is_wrap_q_reg),
        .I5(din[6]),
        .O(p_0_out[21]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_7__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_0 [0]),
        .I3(\gpr1.dout_i_reg[15]_1 [2]),
        .I4(access_is_wrap_q_reg),
        .I5(din[5]),
        .O(p_0_out[20]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_8__0
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_3 ),
        .I3(\gpr1.dout_i_reg[15]_1 [1]),
        .I4(access_is_wrap_q_reg),
        .I5(din[4]),
        .O(p_0_out[19]));
  LUT6 #(
    .INIT(64'h0000000000007500)) 
    fifo_gen_inst_i_9
       (.I0(split_ongoing_reg),
        .I1(si_full_size_q),
        .I2(\gpr1.dout_i_reg[15]_2 ),
        .I3(\gpr1.dout_i_reg[15]_1 [0]),
        .I4(access_is_wrap_q_reg),
        .I5(din[3]),
        .O(p_0_out[18]));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT3 #(
    .INIT(8'h20)) 
    first_word_i_1
       (.I0(s_axi_wvalid),
        .I1(empty),
        .I2(m_axi_wready),
        .O(s_axi_wvalid_0));
  LUT6 #(
    .INIT(64'hF704F7F708FB0808)) 
    \m_axi_awlen[0]_INST_0 
       (.I0(\m_axi_awlen[7] [0]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .I4(\m_axi_awlen[4] [0]),
        .I5(\m_axi_awlen[0]_INST_0_i_1_n_0 ),
        .O(access_fit_mi_side_q_reg[0]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_awlen[0]_INST_0_i_1 
       (.I0(\m_axi_awlen[7]_0 [0]),
        .I1(din[7]),
        .I2(\m_axi_awlen[7]_INST_0_i_6_1 [0]),
        .I3(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
        .I4(\m_axi_awlen[1]_INST_0_i_3_n_0 ),
        .O(\m_axi_awlen[0]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0BFBF404F4040BFB)) 
    \m_axi_awlen[1]_INST_0 
       (.I0(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .I1(\m_axi_awlen[4] [1]),
        .I2(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_awlen[7] [1]),
        .I4(\m_axi_awlen[1]_INST_0_i_1_n_0 ),
        .I5(\m_axi_awlen[1]_INST_0_i_2_n_0 ),
        .O(access_fit_mi_side_q_reg[1]));
  LUT6 #(
    .INIT(64'h00000000001DFF1D)) 
    \m_axi_awlen[1]_INST_0_i_1 
       (.I0(\m_axi_awlen[1]_INST_0_i_3_n_0 ),
        .I1(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
        .I2(\m_axi_awlen[7]_INST_0_i_6_1 [0]),
        .I3(din[7]),
        .I4(\m_axi_awlen[7]_0 [0]),
        .I5(\m_axi_awlen[1]_INST_0_i_4_n_0 ),
        .O(\m_axi_awlen[1]_INST_0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h47444777)) 
    \m_axi_awlen[1]_INST_0_i_2 
       (.I0(\m_axi_awlen[7]_0 [1]),
        .I1(din[7]),
        .I2(\m_axi_awlen[7]_INST_0_i_6_1 [1]),
        .I3(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
        .I4(\m_axi_awlen[1]_INST_0_i_5_n_0 ),
        .O(\m_axi_awlen[1]_INST_0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_awlen[1]_INST_0_i_3 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_0 [0]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[4]_INST_0_i_3_0 [0]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_awlen[1]_INST_0_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT5 #(
    .INIT(32'hF704F7F7)) 
    \m_axi_awlen[1]_INST_0_i_4 
       (.I0(\m_axi_awlen[7] [0]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .I4(\m_axi_awlen[4] [0]),
        .O(\m_axi_awlen[1]_INST_0_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_awlen[1]_INST_0_i_5 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_0 [1]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[4]_INST_0_i_3_0 [1]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_awlen[1]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h95959A956A6A656A)) 
    \m_axi_awlen[2]_INST_0 
       (.I0(\m_axi_awlen[2]_INST_0_i_1_n_0 ),
        .I1(\m_axi_awlen[7] [2]),
        .I2(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_awlen[4] [2]),
        .I4(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .I5(\m_axi_awlen[2]_INST_0_i_2_n_0 ),
        .O(access_fit_mi_side_q_reg[2]));
  LUT6 #(
    .INIT(64'hFFFF88B888B80000)) 
    \m_axi_awlen[2]_INST_0_i_1 
       (.I0(\m_axi_awlen[7] [1]),
        .I1(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
        .I2(\m_axi_awlen[4] [1]),
        .I3(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .I4(\m_axi_awlen[1]_INST_0_i_1_n_0 ),
        .I5(\m_axi_awlen[1]_INST_0_i_2_n_0 ),
        .O(\m_axi_awlen[2]_INST_0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B8B8)) 
    \m_axi_awlen[2]_INST_0_i_2 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_1 [2]),
        .I1(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
        .I2(\m_axi_awlen[2]_INST_0_i_3_n_0 ),
        .I3(\m_axi_awlen[7]_0 [2]),
        .I4(din[7]),
        .O(\m_axi_awlen[2]_INST_0_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_awlen[2]_INST_0_i_3 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_0 [2]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[4]_INST_0_i_3_0 [2]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_awlen[2]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h95959A956A6A656A)) 
    \m_axi_awlen[3]_INST_0 
       (.I0(\m_axi_awlen[3]_INST_0_i_1_n_0 ),
        .I1(\m_axi_awlen[7] [3]),
        .I2(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_awlen[4] [3]),
        .I4(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .I5(\m_axi_awlen[3]_INST_0_i_2_n_0 ),
        .O(access_fit_mi_side_q_reg[3]));
  LUT5 #(
    .INIT(32'hBBB2B222)) 
    \m_axi_awlen[3]_INST_0_i_1 
       (.I0(\m_axi_awlen[3]_INST_0_i_3_n_0 ),
        .I1(\m_axi_awlen[2]_INST_0_i_2_n_0 ),
        .I2(\m_axi_awlen[1]_INST_0_i_2_n_0 ),
        .I3(\m_axi_awlen[1]_INST_0_i_1_n_0 ),
        .I4(\m_axi_awlen[3]_INST_0_i_4_n_0 ),
        .O(\m_axi_awlen[3]_INST_0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B8B8)) 
    \m_axi_awlen[3]_INST_0_i_2 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_1 [3]),
        .I1(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
        .I2(\m_axi_awlen[3]_INST_0_i_5_n_0 ),
        .I3(\m_axi_awlen[7]_0 [3]),
        .I4(din[7]),
        .O(\m_axi_awlen[3]_INST_0_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \m_axi_awlen[3]_INST_0_i_3 
       (.I0(\m_axi_awlen[7] [2]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[4] [2]),
        .I4(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .O(\m_axi_awlen[3]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \m_axi_awlen[3]_INST_0_i_4 
       (.I0(\m_axi_awlen[7] [1]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[4] [1]),
        .I4(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .O(\m_axi_awlen[3]_INST_0_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_awlen[3]_INST_0_i_5 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_0 [3]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[4]_INST_0_i_3_0 [3]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_awlen[3]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h95959A956A6A656A)) 
    \m_axi_awlen[4]_INST_0 
       (.I0(\m_axi_awlen[4]_INST_0_i_1_n_0 ),
        .I1(\m_axi_awlen[7] [4]),
        .I2(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
        .I3(\m_axi_awlen[4] [4]),
        .I4(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .I5(\m_axi_awlen[4]_INST_0_i_3_n_0 ),
        .O(access_fit_mi_side_q_reg[4]));
  LUT6 #(
    .INIT(64'h88B8FFFF000088B8)) 
    \m_axi_awlen[4]_INST_0_i_1 
       (.I0(\m_axi_awlen[7] [3]),
        .I1(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
        .I2(\m_axi_awlen[4] [3]),
        .I3(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .I4(\m_axi_awlen[3]_INST_0_i_2_n_0 ),
        .I5(\m_axi_awlen[3]_INST_0_i_1_n_0 ),
        .O(\m_axi_awlen[4]_INST_0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT5 #(
    .INIT(32'h0000FD0D)) 
    \m_axi_awlen[4]_INST_0_i_2 
       (.I0(access_is_incr_q),
        .I1(din[7]),
        .I2(incr_need_to_split_q),
        .I3(split_ongoing),
        .I4(fix_need_to_split_q),
        .O(\m_axi_awlen[4]_INST_0_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFF00B8B8)) 
    \m_axi_awlen[4]_INST_0_i_3 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_1 [4]),
        .I1(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
        .I2(\m_axi_awlen[4]_INST_0_i_4_n_0 ),
        .I3(\m_axi_awlen[7]_0 [4]),
        .I4(din[7]),
        .O(\m_axi_awlen[4]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFF00BFBF)) 
    \m_axi_awlen[4]_INST_0_i_4 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_0 [4]),
        .I1(access_is_wrap_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[4]_INST_0_i_3_0 [4]),
        .I4(fix_need_to_split_q),
        .O(\m_axi_awlen[4]_INST_0_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT5 #(
    .INIT(32'h5955A6AA)) 
    \m_axi_awlen[5]_INST_0 
       (.I0(\m_axi_awlen[7]_INST_0_i_3_n_0 ),
        .I1(\m_axi_awlen[7] [5]),
        .I2(split_ongoing),
        .I3(wrap_need_to_split_q),
        .I4(\m_axi_awlen[7]_INST_0_i_4_n_0 ),
        .O(access_fit_mi_side_q_reg[5]));
  LUT6 #(
    .INIT(64'hD42BBBBB2BD44444)) 
    \m_axi_awlen[6]_INST_0 
       (.I0(\m_axi_awlen[7]_INST_0_i_4_n_0 ),
        .I1(\m_axi_awlen[7]_INST_0_i_3_n_0 ),
        .I2(\m_axi_awlen[7] [5]),
        .I3(\m_axi_awlen[7] [6]),
        .I4(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
        .I5(\m_axi_awlen[7]_INST_0_i_5_n_0 ),
        .O(access_fit_mi_side_q_reg[6]));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \m_axi_awlen[6]_INST_0_i_1 
       (.I0(wrap_need_to_split_q),
        .I1(split_ongoing),
        .O(\m_axi_awlen[6]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7F57150180A8EAFE)) 
    \m_axi_awlen[7]_INST_0 
       (.I0(\m_axi_awlen[7]_INST_0_i_1_n_0 ),
        .I1(\m_axi_awlen[7]_INST_0_i_2_n_0 ),
        .I2(\m_axi_awlen[7]_INST_0_i_3_n_0 ),
        .I3(\m_axi_awlen[7]_INST_0_i_4_n_0 ),
        .I4(\m_axi_awlen[7]_INST_0_i_5_n_0 ),
        .I5(\m_axi_awlen[7]_INST_0_i_6_n_0 ),
        .O(access_fit_mi_side_q_reg[7]));
  LUT3 #(
    .INIT(8'h20)) 
    \m_axi_awlen[7]_INST_0_i_1 
       (.I0(\m_axi_awlen[7] [6]),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .O(\m_axi_awlen[7]_INST_0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT4 #(
    .INIT(16'h4555)) 
    \m_axi_awlen[7]_INST_0_i_10 
       (.I0(fix_need_to_split_q),
        .I1(\m_axi_awlen[7]_INST_0_i_6_0 [5]),
        .I2(access_is_wrap_q),
        .I3(split_ongoing),
        .O(\m_axi_awlen[7]_INST_0_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT4 #(
    .INIT(16'h4555)) 
    \m_axi_awlen[7]_INST_0_i_11 
       (.I0(fix_need_to_split_q),
        .I1(\m_axi_awlen[7]_INST_0_i_6_0 [6]),
        .I2(access_is_wrap_q),
        .I3(split_ongoing),
        .O(\m_axi_awlen[7]_INST_0_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h8B888B8B8B8B8B8B)) 
    \m_axi_awlen[7]_INST_0_i_12 
       (.I0(\m_axi_awlen[7]_INST_0_i_6_1 [7]),
        .I1(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
        .I2(fix_need_to_split_q),
        .I3(\m_axi_awlen[7]_INST_0_i_6_0 [7]),
        .I4(access_is_wrap_q),
        .I5(split_ongoing),
        .O(\m_axi_awlen[7]_INST_0_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \m_axi_awlen[7]_INST_0_i_13 
       (.I0(access_is_wrap_q),
        .I1(legal_wrap_len_q),
        .I2(split_ongoing),
        .O(\m_axi_awlen[7]_INST_0_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \m_axi_awlen[7]_INST_0_i_16 
       (.I0(access_is_wrap_q),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .O(\m_axi_awlen[7]_INST_0_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \m_axi_awlen[7]_INST_0_i_2 
       (.I0(\m_axi_awlen[7] [5]),
        .I1(split_ongoing),
        .I2(wrap_need_to_split_q),
        .O(\m_axi_awlen[7]_INST_0_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB2BB22B2)) 
    \m_axi_awlen[7]_INST_0_i_3 
       (.I0(\m_axi_awlen[7]_INST_0_i_7_n_0 ),
        .I1(\m_axi_awlen[4]_INST_0_i_3_n_0 ),
        .I2(\m_axi_awlen[3]_INST_0_i_1_n_0 ),
        .I3(\m_axi_awlen[3]_INST_0_i_2_n_0 ),
        .I4(\m_axi_awlen[7]_INST_0_i_8_n_0 ),
        .O(\m_axi_awlen[7]_INST_0_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_awlen[7]_INST_0_i_4 
       (.I0(\m_axi_awlen[7]_0 [5]),
        .I1(din[7]),
        .I2(\m_axi_awlen[7]_INST_0_i_6_1 [5]),
        .I3(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
        .I4(\m_axi_awlen[7]_INST_0_i_10_n_0 ),
        .O(\m_axi_awlen[7]_INST_0_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \m_axi_awlen[7]_INST_0_i_5 
       (.I0(\m_axi_awlen[7]_0 [6]),
        .I1(din[7]),
        .I2(\m_axi_awlen[7]_INST_0_i_6_1 [6]),
        .I3(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
        .I4(\m_axi_awlen[7]_INST_0_i_11_n_0 ),
        .O(\m_axi_awlen[7]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hDFDFDF202020DF20)) 
    \m_axi_awlen[7]_INST_0_i_6 
       (.I0(wrap_need_to_split_q),
        .I1(split_ongoing),
        .I2(\m_axi_awlen[7] [7]),
        .I3(\m_axi_awlen[7]_INST_0_i_12_n_0 ),
        .I4(din[7]),
        .I5(\m_axi_awlen[7]_0 [7]),
        .O(\m_axi_awlen[7]_INST_0_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \m_axi_awlen[7]_INST_0_i_7 
       (.I0(\m_axi_awlen[7] [4]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[4] [4]),
        .I4(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .O(\m_axi_awlen[7]_INST_0_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \m_axi_awlen[7]_INST_0_i_8 
       (.I0(\m_axi_awlen[7] [3]),
        .I1(wrap_need_to_split_q),
        .I2(split_ongoing),
        .I3(\m_axi_awlen[4] [3]),
        .I4(\m_axi_awlen[4]_INST_0_i_2_n_0 ),
        .O(\m_axi_awlen[7]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFAAFFAABFAAFFAA)) 
    \m_axi_awlen[7]_INST_0_i_9 
       (.I0(\m_axi_awlen[7]_INST_0_i_13_n_0 ),
        .I1(incr_need_to_split_q),
        .I2(\m_axi_awlen[7]_INST_0_i_5_0 ),
        .I3(access_is_incr_q),
        .I4(\m_axi_awlen[7]_INST_0_i_5_1 ),
        .I5(\m_axi_awlen[7]_INST_0_i_16_n_0 ),
        .O(\m_axi_awlen[7]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_awsize[0]_INST_0 
       (.I0(din[7]),
        .I1(din[0]),
        .O(access_fit_mi_side_q_reg[8]));
  LUT2 #(
    .INIT(4'hB)) 
    \m_axi_awsize[1]_INST_0 
       (.I0(din[1]),
        .I1(din[7]),
        .O(access_fit_mi_side_q_reg[9]));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \m_axi_awsize[2]_INST_0 
       (.I0(din[7]),
        .I1(din[2]),
        .O(access_fit_mi_side_q_reg[10]));
  LUT6 #(
    .INIT(64'h888A888A888A8888)) 
    m_axi_awvalid_INST_0
       (.I0(command_ongoing),
        .I1(cmd_push_block),
        .I2(full_0),
        .I3(full),
        .I4(m_axi_awvalid_INST_0_i_1_n_0),
        .I5(cmd_b_empty),
        .O(command_ongoing_reg));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    m_axi_awvalid_INST_0_i_1
       (.I0(m_axi_awvalid_INST_0_i_2_n_0),
        .I1(m_axi_awvalid_INST_0_i_3_n_0),
        .I2(m_axi_awvalid_INST_0_i_4_n_0),
        .I3(m_axi_awvalid_INST_0_i_5_n_0),
        .I4(m_axi_awvalid_INST_0_i_6_n_0),
        .I5(m_axi_awvalid_INST_0_i_7_n_0),
        .O(m_axi_awvalid_INST_0_i_1_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    m_axi_awvalid_INST_0_i_2
       (.I0(s_axi_bid[15]),
        .I1(m_axi_awvalid_INST_0_i_1_0[15]),
        .O(m_axi_awvalid_INST_0_i_2_n_0));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    m_axi_awvalid_INST_0_i_3
       (.I0(m_axi_awvalid_INST_0_i_1_0[6]),
        .I1(s_axi_bid[6]),
        .I2(s_axi_bid[7]),
        .I3(m_axi_awvalid_INST_0_i_1_0[7]),
        .I4(s_axi_bid[8]),
        .I5(m_axi_awvalid_INST_0_i_1_0[8]),
        .O(m_axi_awvalid_INST_0_i_3_n_0));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    m_axi_awvalid_INST_0_i_4
       (.I0(m_axi_awvalid_INST_0_i_1_0[9]),
        .I1(s_axi_bid[9]),
        .I2(s_axi_bid[10]),
        .I3(m_axi_awvalid_INST_0_i_1_0[10]),
        .I4(s_axi_bid[11]),
        .I5(m_axi_awvalid_INST_0_i_1_0[11]),
        .O(m_axi_awvalid_INST_0_i_4_n_0));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    m_axi_awvalid_INST_0_i_5
       (.I0(m_axi_awvalid_INST_0_i_1_0[0]),
        .I1(s_axi_bid[0]),
        .I2(s_axi_bid[1]),
        .I3(m_axi_awvalid_INST_0_i_1_0[1]),
        .I4(s_axi_bid[2]),
        .I5(m_axi_awvalid_INST_0_i_1_0[2]),
        .O(m_axi_awvalid_INST_0_i_5_n_0));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    m_axi_awvalid_INST_0_i_6
       (.I0(m_axi_awvalid_INST_0_i_1_0[3]),
        .I1(s_axi_bid[3]),
        .I2(s_axi_bid[4]),
        .I3(m_axi_awvalid_INST_0_i_1_0[4]),
        .I4(s_axi_bid[5]),
        .I5(m_axi_awvalid_INST_0_i_1_0[5]),
        .O(m_axi_awvalid_INST_0_i_6_n_0));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    m_axi_awvalid_INST_0_i_7
       (.I0(m_axi_awvalid_INST_0_i_1_0[12]),
        .I1(s_axi_bid[12]),
        .I2(s_axi_bid[13]),
        .I3(m_axi_awvalid_INST_0_i_1_0[13]),
        .I4(s_axi_bid[14]),
        .I5(m_axi_awvalid_INST_0_i_1_0[14]),
        .O(m_axi_awvalid_INST_0_i_7_n_0));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_axi_wdata[0]_INST_0 
       (.I0(s_axi_wdata[0]),
        .I1(s_axi_wdata[32]),
        .I2(s_axi_wdata[96]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[64]),
        .O(m_axi_wdata[0]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[10]_INST_0 
       (.I0(s_axi_wdata[42]),
        .I1(s_axi_wdata[106]),
        .I2(s_axi_wdata[10]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[74]),
        .O(m_axi_wdata[10]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[11]_INST_0 
       (.I0(s_axi_wdata[43]),
        .I1(s_axi_wdata[107]),
        .I2(s_axi_wdata[11]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[75]),
        .O(m_axi_wdata[11]));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_axi_wdata[12]_INST_0 
       (.I0(s_axi_wdata[12]),
        .I1(s_axi_wdata[44]),
        .I2(s_axi_wdata[108]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[76]),
        .O(m_axi_wdata[12]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[13]_INST_0 
       (.I0(s_axi_wdata[45]),
        .I1(s_axi_wdata[109]),
        .I2(s_axi_wdata[13]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[77]),
        .O(m_axi_wdata[13]));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_axi_wdata[14]_INST_0 
       (.I0(s_axi_wdata[14]),
        .I1(s_axi_wdata[46]),
        .I2(s_axi_wdata[110]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[78]),
        .O(m_axi_wdata[14]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[15]_INST_0 
       (.I0(s_axi_wdata[47]),
        .I1(s_axi_wdata[111]),
        .I2(s_axi_wdata[15]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[79]),
        .O(m_axi_wdata[15]));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_axi_wdata[16]_INST_0 
       (.I0(s_axi_wdata[16]),
        .I1(s_axi_wdata[48]),
        .I2(s_axi_wdata[112]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[80]),
        .O(m_axi_wdata[16]));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \m_axi_wdata[17]_INST_0 
       (.I0(s_axi_wdata[17]),
        .I1(s_axi_wdata[49]),
        .I2(s_axi_wdata[81]),
        .I3(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I5(s_axi_wdata[113]),
        .O(m_axi_wdata[17]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[18]_INST_0 
       (.I0(s_axi_wdata[50]),
        .I1(s_axi_wdata[114]),
        .I2(s_axi_wdata[18]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[82]),
        .O(m_axi_wdata[18]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[19]_INST_0 
       (.I0(s_axi_wdata[51]),
        .I1(s_axi_wdata[115]),
        .I2(s_axi_wdata[19]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[83]),
        .O(m_axi_wdata[19]));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \m_axi_wdata[1]_INST_0 
       (.I0(s_axi_wdata[1]),
        .I1(s_axi_wdata[33]),
        .I2(s_axi_wdata[65]),
        .I3(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I5(s_axi_wdata[97]),
        .O(m_axi_wdata[1]));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_axi_wdata[20]_INST_0 
       (.I0(s_axi_wdata[20]),
        .I1(s_axi_wdata[52]),
        .I2(s_axi_wdata[116]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[84]),
        .O(m_axi_wdata[20]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[21]_INST_0 
       (.I0(s_axi_wdata[53]),
        .I1(s_axi_wdata[117]),
        .I2(s_axi_wdata[21]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[85]),
        .O(m_axi_wdata[21]));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_axi_wdata[22]_INST_0 
       (.I0(s_axi_wdata[22]),
        .I1(s_axi_wdata[54]),
        .I2(s_axi_wdata[118]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[86]),
        .O(m_axi_wdata[22]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[23]_INST_0 
       (.I0(s_axi_wdata[55]),
        .I1(s_axi_wdata[119]),
        .I2(s_axi_wdata[23]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[87]),
        .O(m_axi_wdata[23]));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_axi_wdata[24]_INST_0 
       (.I0(s_axi_wdata[24]),
        .I1(s_axi_wdata[56]),
        .I2(s_axi_wdata[120]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[88]),
        .O(m_axi_wdata[24]));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \m_axi_wdata[25]_INST_0 
       (.I0(s_axi_wdata[25]),
        .I1(s_axi_wdata[57]),
        .I2(s_axi_wdata[89]),
        .I3(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I5(s_axi_wdata[121]),
        .O(m_axi_wdata[25]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[26]_INST_0 
       (.I0(s_axi_wdata[58]),
        .I1(s_axi_wdata[122]),
        .I2(s_axi_wdata[26]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[90]),
        .O(m_axi_wdata[26]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[27]_INST_0 
       (.I0(s_axi_wdata[59]),
        .I1(s_axi_wdata[123]),
        .I2(s_axi_wdata[27]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[91]),
        .O(m_axi_wdata[27]));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_axi_wdata[28]_INST_0 
       (.I0(s_axi_wdata[28]),
        .I1(s_axi_wdata[60]),
        .I2(s_axi_wdata[124]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[92]),
        .O(m_axi_wdata[28]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[29]_INST_0 
       (.I0(s_axi_wdata[61]),
        .I1(s_axi_wdata[125]),
        .I2(s_axi_wdata[29]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[93]),
        .O(m_axi_wdata[29]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[2]_INST_0 
       (.I0(s_axi_wdata[34]),
        .I1(s_axi_wdata[98]),
        .I2(s_axi_wdata[2]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[66]),
        .O(m_axi_wdata[2]));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_axi_wdata[30]_INST_0 
       (.I0(s_axi_wdata[30]),
        .I1(s_axi_wdata[62]),
        .I2(s_axi_wdata[126]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[94]),
        .O(m_axi_wdata[30]));
  LUT6 #(
    .INIT(64'hF0CCAAFFF0CCAA00)) 
    \m_axi_wdata[31]_INST_0 
       (.I0(s_axi_wdata[63]),
        .I1(s_axi_wdata[95]),
        .I2(s_axi_wdata[31]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[127]),
        .O(m_axi_wdata[31]));
  LUT5 #(
    .INIT(32'hD42B2BD4)) 
    \m_axi_wdata[31]_INST_0_i_1 
       (.I0(\m_axi_wdata[31]_INST_0_i_3_n_0 ),
        .I1(\USE_WRITE.wr_cmd_offset [2]),
        .I2(\current_word_1_reg[2] ),
        .I3(m_axi_wstrb_3_sn_1),
        .I4(\USE_WRITE.wr_cmd_offset [3]),
        .O(\m_axi_wdata[31]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAA955595556AAA6)) 
    \m_axi_wdata[31]_INST_0_i_2 
       (.I0(\m_axi_wdata[31]_INST_0_i_3_n_0 ),
        .I1(\current_word_1_reg[3] [1]),
        .I2(dout[15]),
        .I3(first_mi_word),
        .I4(dout[13]),
        .I5(\USE_WRITE.wr_cmd_offset [2]),
        .O(\m_axi_wdata[31]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00001DFF1DFFFFFF)) 
    \m_axi_wdata[31]_INST_0_i_3 
       (.I0(dout[11]),
        .I1(\m_axi_wdata[31]_INST_0_i_6_n_0 ),
        .I2(\current_word_1_reg[3] [0]),
        .I3(\USE_WRITE.wr_cmd_offset [0]),
        .I4(\USE_WRITE.wr_cmd_offset [1]),
        .I5(\current_word_1_reg[1] ),
        .O(\m_axi_wdata[31]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \m_axi_wdata[31]_INST_0_i_6 
       (.I0(dout[15]),
        .I1(first_mi_word),
        .O(\m_axi_wdata[31]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[3]_INST_0 
       (.I0(s_axi_wdata[35]),
        .I1(s_axi_wdata[99]),
        .I2(s_axi_wdata[3]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[67]),
        .O(m_axi_wdata[3]));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_axi_wdata[4]_INST_0 
       (.I0(s_axi_wdata[4]),
        .I1(s_axi_wdata[36]),
        .I2(s_axi_wdata[100]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[68]),
        .O(m_axi_wdata[4]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[5]_INST_0 
       (.I0(s_axi_wdata[37]),
        .I1(s_axi_wdata[101]),
        .I2(s_axi_wdata[5]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[69]),
        .O(m_axi_wdata[5]));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_axi_wdata[6]_INST_0 
       (.I0(s_axi_wdata[6]),
        .I1(s_axi_wdata[38]),
        .I2(s_axi_wdata[102]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[70]),
        .O(m_axi_wdata[6]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \m_axi_wdata[7]_INST_0 
       (.I0(s_axi_wdata[39]),
        .I1(s_axi_wdata[103]),
        .I2(s_axi_wdata[7]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[71]),
        .O(m_axi_wdata[7]));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \m_axi_wdata[8]_INST_0 
       (.I0(s_axi_wdata[8]),
        .I1(s_axi_wdata[40]),
        .I2(s_axi_wdata[104]),
        .I3(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wdata[72]),
        .O(m_axi_wdata[8]));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \m_axi_wdata[9]_INST_0 
       (.I0(s_axi_wdata[9]),
        .I1(s_axi_wdata[41]),
        .I2(s_axi_wdata[73]),
        .I3(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I4(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I5(s_axi_wdata[105]),
        .O(m_axi_wdata[9]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \m_axi_wstrb[0]_INST_0 
       (.I0(s_axi_wstrb[0]),
        .I1(s_axi_wstrb[4]),
        .I2(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I3(s_axi_wstrb[8]),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wstrb[12]),
        .O(m_axi_wstrb[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \m_axi_wstrb[1]_INST_0 
       (.I0(s_axi_wstrb[1]),
        .I1(s_axi_wstrb[5]),
        .I2(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I3(s_axi_wstrb[9]),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wstrb[13]),
        .O(m_axi_wstrb[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \m_axi_wstrb[2]_INST_0 
       (.I0(s_axi_wstrb[2]),
        .I1(s_axi_wstrb[6]),
        .I2(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I3(s_axi_wstrb[10]),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wstrb[14]),
        .O(m_axi_wstrb[2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \m_axi_wstrb[3]_INST_0 
       (.I0(s_axi_wstrb[3]),
        .I1(s_axi_wstrb[7]),
        .I2(\m_axi_wdata[31]_INST_0_i_1_n_0 ),
        .I3(s_axi_wstrb[11]),
        .I4(\m_axi_wdata[31]_INST_0_i_2_n_0 ),
        .I5(s_axi_wstrb[15]),
        .O(m_axi_wstrb[3]));
  LUT2 #(
    .INIT(4'h2)) 
    m_axi_wvalid_INST_0
       (.I0(s_axi_wvalid),
        .I1(empty),
        .O(m_axi_wvalid));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \queue_id[15]_i_1 
       (.I0(command_ongoing_reg),
        .I1(cmd_push_block),
        .O(E));
  LUT6 #(
    .INIT(64'h4444444044444444)) 
    s_axi_wready_INST_0
       (.I0(empty),
        .I1(m_axi_wready),
        .I2(s_axi_wready_0),
        .I3(\USE_WRITE.wr_cmd_mirror ),
        .I4(dout[15]),
        .I5(s_axi_wready_INST_0_i_1_n_0),
        .O(s_axi_wready));
  LUT6 #(
    .INIT(64'hFEFEFEFEFCCCCCCC)) 
    s_axi_wready_INST_0_i_1
       (.I0(\goreg_dm.dout_i_reg[17] [3]),
        .I1(s_axi_wready_INST_0_i_2_n_0),
        .I2(\goreg_dm.dout_i_reg[17] [2]),
        .I3(\USE_WRITE.wr_cmd_size [0]),
        .I4(\USE_WRITE.wr_cmd_size [1]),
        .I5(\USE_WRITE.wr_cmd_size [2]),
        .O(s_axi_wready_INST_0_i_1_n_0));
  LUT5 #(
    .INIT(32'hFFFCA8A8)) 
    s_axi_wready_INST_0_i_2
       (.I0(\goreg_dm.dout_i_reg[17] [1]),
        .I1(\USE_WRITE.wr_cmd_size [1]),
        .I2(\USE_WRITE.wr_cmd_size [2]),
        .I3(\USE_WRITE.wr_cmd_size [0]),
        .I4(\goreg_dm.dout_i_reg[17] [0]),
        .O(s_axi_wready_INST_0_i_2_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    split_ongoing_i_1
       (.I0(m_axi_awready),
        .I1(command_ongoing_reg),
        .O(m_axi_awready_0));
endmodule

(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_29_a_downsizer" *) 
module design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_a_downsizer
   (dout,
    empty,
    SR,
    \goreg_dm.dout_i_reg[28] ,
    din,
    S_AXI_AREADY_I_reg_0,
    areset_d,
    command_ongoing_reg_0,
    s_axi_bid,
    m_axi_awlock,
    m_axi_awaddr,
    m_axi_wvalid,
    s_axi_wready,
    E,
    m_axi_awburst,
    m_axi_wdata,
    m_axi_wstrb,
    D,
    \areset_d_reg[0]_0 ,
    m_axi_awcache,
    m_axi_awprot,
    m_axi_awregion,
    m_axi_awqos,
    CLK,
    \USE_WRITE.wr_cmd_b_ready ,
    s_axi_awlock,
    s_axi_awsize,
    s_axi_awlen,
    s_axi_awburst,
    s_axi_awvalid,
    m_axi_awready,
    out,
    s_axi_awaddr,
    s_axi_wvalid,
    m_axi_wready,
    s_axi_wready_0,
    s_axi_wdata,
    s_axi_wstrb,
    Q,
    first_mi_word,
    \current_word_1_reg[2] ,
    m_axi_wstrb_3_sp_1,
    \current_word_1_reg[1] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1_reg[3] ,
    S_AXI_AREADY_I_reg_1,
    S_AXI_AREADY_I_reg_2,
    s_axi_arvalid,
    s_axi_awid,
    s_axi_awcache,
    s_axi_awprot,
    s_axi_awregion,
    s_axi_awqos);
  output [4:0]dout;
  output empty;
  output [0:0]SR;
  output [15:0]\goreg_dm.dout_i_reg[28] ;
  output [10:0]din;
  output S_AXI_AREADY_I_reg_0;
  output [1:0]areset_d;
  output command_ongoing_reg_0;
  output [15:0]s_axi_bid;
  output [0:0]m_axi_awlock;
  output [39:0]m_axi_awaddr;
  output m_axi_wvalid;
  output s_axi_wready;
  output [0:0]E;
  output [1:0]m_axi_awburst;
  output [31:0]m_axi_wdata;
  output [3:0]m_axi_wstrb;
  output [3:0]D;
  output \areset_d_reg[0]_0 ;
  output [3:0]m_axi_awcache;
  output [2:0]m_axi_awprot;
  output [3:0]m_axi_awregion;
  output [3:0]m_axi_awqos;
  input CLK;
  input \USE_WRITE.wr_cmd_b_ready ;
  input [0:0]s_axi_awlock;
  input [2:0]s_axi_awsize;
  input [7:0]s_axi_awlen;
  input [1:0]s_axi_awburst;
  input s_axi_awvalid;
  input m_axi_awready;
  input out;
  input [39:0]s_axi_awaddr;
  input s_axi_wvalid;
  input m_axi_wready;
  input s_axi_wready_0;
  input [127:0]s_axi_wdata;
  input [15:0]s_axi_wstrb;
  input [2:0]Q;
  input first_mi_word;
  input \current_word_1_reg[2] ;
  input m_axi_wstrb_3_sp_1;
  input \current_word_1_reg[1] ;
  input \current_word_1_reg[1]_0 ;
  input \current_word_1_reg[3] ;
  input S_AXI_AREADY_I_reg_1;
  input [0:0]S_AXI_AREADY_I_reg_2;
  input s_axi_arvalid;
  input [15:0]s_axi_awid;
  input [3:0]s_axi_awcache;
  input [2:0]s_axi_awprot;
  input [3:0]s_axi_awregion;
  input [3:0]s_axi_awqos;

  wire CLK;
  wire [3:0]D;
  wire [0:0]E;
  wire [2:0]Q;
  wire [0:0]SR;
  wire \S_AXI_AADDR_Q_reg_n_0_[0] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[10] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[11] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[12] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[13] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[14] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[15] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[16] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[17] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[18] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[19] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[1] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[20] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[21] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[22] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[23] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[24] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[25] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[26] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[27] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[28] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[29] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[2] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[30] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[31] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[32] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[33] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[34] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[35] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[36] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[37] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[38] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[39] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[3] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[4] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[5] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[6] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[7] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[8] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[9] ;
  wire [1:0]S_AXI_ABURST_Q;
  wire [15:0]S_AXI_AID_Q;
  wire \S_AXI_ALEN_Q_reg_n_0_[4] ;
  wire \S_AXI_ALEN_Q_reg_n_0_[5] ;
  wire \S_AXI_ALEN_Q_reg_n_0_[6] ;
  wire \S_AXI_ALEN_Q_reg_n_0_[7] ;
  wire [0:0]S_AXI_ALOCK_Q;
  wire S_AXI_AREADY_I_reg_0;
  wire S_AXI_AREADY_I_reg_1;
  wire [0:0]S_AXI_AREADY_I_reg_2;
  wire [2:0]S_AXI_ASIZE_Q;
  wire \USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0 ;
  wire [5:0]\USE_B_CHANNEL.cmd_b_depth_reg ;
  wire \USE_B_CHANNEL.cmd_b_empty_i_i_2_n_0 ;
  wire \USE_B_CHANNEL.cmd_b_queue_n_10 ;
  wire \USE_B_CHANNEL.cmd_b_queue_n_11 ;
  wire \USE_B_CHANNEL.cmd_b_queue_n_9 ;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire access_fit_mi_side_q;
  wire access_is_fix;
  wire access_is_fix_q;
  wire access_is_incr;
  wire access_is_incr_q;
  wire access_is_wrap;
  wire access_is_wrap_q;
  wire [1:0]areset_d;
  wire \areset_d_reg[0]_0 ;
  wire cmd_b_empty;
  wire cmd_b_push;
  wire cmd_b_push_block;
  wire cmd_mask_q;
  wire \cmd_mask_q[0]_i_1_n_0 ;
  wire \cmd_mask_q[1]_i_1_n_0 ;
  wire \cmd_mask_q[2]_i_1_n_0 ;
  wire \cmd_mask_q[3]_i_1_n_0 ;
  wire \cmd_mask_q_reg_n_0_[0] ;
  wire \cmd_mask_q_reg_n_0_[1] ;
  wire \cmd_mask_q_reg_n_0_[2] ;
  wire \cmd_mask_q_reg_n_0_[3] ;
  wire cmd_push;
  wire cmd_push_block;
  wire cmd_queue_n_28;
  wire cmd_queue_n_29;
  wire cmd_queue_n_30;
  wire cmd_queue_n_31;
  wire cmd_queue_n_32;
  wire cmd_queue_n_33;
  wire cmd_queue_n_35;
  wire cmd_queue_n_36;
  wire cmd_queue_n_37;
  wire cmd_queue_n_38;
  wire cmd_queue_n_41;
  wire cmd_queue_n_42;
  wire cmd_queue_n_86;
  wire cmd_split_i;
  wire command_ongoing;
  wire command_ongoing_reg_0;
  wire \current_word_1_reg[1] ;
  wire \current_word_1_reg[1]_0 ;
  wire \current_word_1_reg[2] ;
  wire \current_word_1_reg[3] ;
  wire [10:0]din;
  wire [4:0]dout;
  wire [7:0]downsized_len_q;
  wire \downsized_len_q[0]_i_1_n_0 ;
  wire \downsized_len_q[1]_i_1_n_0 ;
  wire \downsized_len_q[2]_i_1_n_0 ;
  wire \downsized_len_q[3]_i_1_n_0 ;
  wire \downsized_len_q[4]_i_1_n_0 ;
  wire \downsized_len_q[5]_i_1_n_0 ;
  wire \downsized_len_q[6]_i_1_n_0 ;
  wire \downsized_len_q[7]_i_1_n_0 ;
  wire \downsized_len_q[7]_i_2_n_0 ;
  wire empty;
  wire first_mi_word;
  wire [4:0]fix_len;
  wire [4:0]fix_len_q;
  wire fix_need_to_split;
  wire fix_need_to_split_q;
  wire [15:0]\goreg_dm.dout_i_reg[28] ;
  wire incr_need_to_split;
  wire incr_need_to_split_q;
  wire \inst/full ;
  wire legal_wrap_len_q;
  wire legal_wrap_len_q_i_1_n_0;
  wire legal_wrap_len_q_i_2_n_0;
  wire legal_wrap_len_q_i_3_n_0;
  wire [39:0]m_axi_awaddr;
  wire [1:0]m_axi_awburst;
  wire [3:0]m_axi_awcache;
  wire [0:0]m_axi_awlock;
  wire [2:0]m_axi_awprot;
  wire [3:0]m_axi_awqos;
  wire m_axi_awready;
  wire [3:0]m_axi_awregion;
  wire [31:0]m_axi_wdata;
  wire m_axi_wready;
  wire [3:0]m_axi_wstrb;
  wire m_axi_wstrb_3_sn_1;
  wire m_axi_wvalid;
  wire [14:0]masked_addr;
  wire [39:0]masked_addr_q;
  wire \masked_addr_q[2]_i_2_n_0 ;
  wire \masked_addr_q[3]_i_2_n_0 ;
  wire \masked_addr_q[3]_i_3_n_0 ;
  wire \masked_addr_q[4]_i_2_n_0 ;
  wire \masked_addr_q[5]_i_2_n_0 ;
  wire \masked_addr_q[6]_i_2_n_0 ;
  wire \masked_addr_q[7]_i_2_n_0 ;
  wire \masked_addr_q[7]_i_3_n_0 ;
  wire \masked_addr_q[8]_i_2_n_0 ;
  wire \masked_addr_q[8]_i_3_n_0 ;
  wire \masked_addr_q[9]_i_2_n_0 ;
  wire [39:2]next_mi_addr;
  wire next_mi_addr0_carry__0_n_0;
  wire next_mi_addr0_carry__0_n_1;
  wire next_mi_addr0_carry__0_n_10;
  wire next_mi_addr0_carry__0_n_11;
  wire next_mi_addr0_carry__0_n_12;
  wire next_mi_addr0_carry__0_n_13;
  wire next_mi_addr0_carry__0_n_14;
  wire next_mi_addr0_carry__0_n_15;
  wire next_mi_addr0_carry__0_n_2;
  wire next_mi_addr0_carry__0_n_3;
  wire next_mi_addr0_carry__0_n_4;
  wire next_mi_addr0_carry__0_n_5;
  wire next_mi_addr0_carry__0_n_6;
  wire next_mi_addr0_carry__0_n_7;
  wire next_mi_addr0_carry__0_n_8;
  wire next_mi_addr0_carry__0_n_9;
  wire next_mi_addr0_carry__1_n_0;
  wire next_mi_addr0_carry__1_n_1;
  wire next_mi_addr0_carry__1_n_10;
  wire next_mi_addr0_carry__1_n_11;
  wire next_mi_addr0_carry__1_n_12;
  wire next_mi_addr0_carry__1_n_13;
  wire next_mi_addr0_carry__1_n_14;
  wire next_mi_addr0_carry__1_n_15;
  wire next_mi_addr0_carry__1_n_2;
  wire next_mi_addr0_carry__1_n_3;
  wire next_mi_addr0_carry__1_n_4;
  wire next_mi_addr0_carry__1_n_5;
  wire next_mi_addr0_carry__1_n_6;
  wire next_mi_addr0_carry__1_n_7;
  wire next_mi_addr0_carry__1_n_8;
  wire next_mi_addr0_carry__1_n_9;
  wire next_mi_addr0_carry__2_n_10;
  wire next_mi_addr0_carry__2_n_11;
  wire next_mi_addr0_carry__2_n_12;
  wire next_mi_addr0_carry__2_n_13;
  wire next_mi_addr0_carry__2_n_14;
  wire next_mi_addr0_carry__2_n_15;
  wire next_mi_addr0_carry__2_n_2;
  wire next_mi_addr0_carry__2_n_3;
  wire next_mi_addr0_carry__2_n_4;
  wire next_mi_addr0_carry__2_n_5;
  wire next_mi_addr0_carry__2_n_6;
  wire next_mi_addr0_carry__2_n_7;
  wire next_mi_addr0_carry__2_n_9;
  wire next_mi_addr0_carry_i_8_n_0;
  wire next_mi_addr0_carry_n_0;
  wire next_mi_addr0_carry_n_1;
  wire next_mi_addr0_carry_n_10;
  wire next_mi_addr0_carry_n_11;
  wire next_mi_addr0_carry_n_12;
  wire next_mi_addr0_carry_n_13;
  wire next_mi_addr0_carry_n_14;
  wire next_mi_addr0_carry_n_15;
  wire next_mi_addr0_carry_n_2;
  wire next_mi_addr0_carry_n_3;
  wire next_mi_addr0_carry_n_4;
  wire next_mi_addr0_carry_n_5;
  wire next_mi_addr0_carry_n_6;
  wire next_mi_addr0_carry_n_7;
  wire next_mi_addr0_carry_n_8;
  wire next_mi_addr0_carry_n_9;
  wire [3:0]num_transactions;
  wire \num_transactions_q[0]_i_2_n_0 ;
  wire \num_transactions_q[1]_i_1_n_0 ;
  wire \num_transactions_q[1]_i_2_n_0 ;
  wire \num_transactions_q[2]_i_1_n_0 ;
  wire \num_transactions_q_reg_n_0_[0] ;
  wire \num_transactions_q_reg_n_0_[1] ;
  wire \num_transactions_q_reg_n_0_[2] ;
  wire \num_transactions_q_reg_n_0_[3] ;
  wire out;
  wire [7:0]p_0_in;
  wire [3:0]p_0_in_0;
  wire [8:2]pre_mi_addr;
  wire [39:9]pre_mi_addr__0;
  wire \pushed_commands[7]_i_1_n_0 ;
  wire \pushed_commands[7]_i_3_n_0 ;
  wire [7:0]pushed_commands_reg;
  wire pushed_new_cmd;
  wire s_axi_arvalid;
  wire [39:0]s_axi_awaddr;
  wire [1:0]s_axi_awburst;
  wire [3:0]s_axi_awcache;
  wire [15:0]s_axi_awid;
  wire [7:0]s_axi_awlen;
  wire [0:0]s_axi_awlock;
  wire [2:0]s_axi_awprot;
  wire [3:0]s_axi_awqos;
  wire [3:0]s_axi_awregion;
  wire [2:0]s_axi_awsize;
  wire s_axi_awvalid;
  wire [15:0]s_axi_bid;
  wire [127:0]s_axi_wdata;
  wire s_axi_wready;
  wire s_axi_wready_0;
  wire [15:0]s_axi_wstrb;
  wire s_axi_wvalid;
  wire si_full_size_q;
  wire si_full_size_q_i_1_n_0;
  wire [6:0]split_addr_mask;
  wire \split_addr_mask_q[2]_i_1_n_0 ;
  wire \split_addr_mask_q_reg_n_0_[0] ;
  wire \split_addr_mask_q_reg_n_0_[10] ;
  wire \split_addr_mask_q_reg_n_0_[1] ;
  wire \split_addr_mask_q_reg_n_0_[2] ;
  wire \split_addr_mask_q_reg_n_0_[3] ;
  wire \split_addr_mask_q_reg_n_0_[4] ;
  wire \split_addr_mask_q_reg_n_0_[5] ;
  wire \split_addr_mask_q_reg_n_0_[6] ;
  wire split_ongoing;
  wire [4:0]unalignment_addr;
  wire [4:0]unalignment_addr_q;
  wire wrap_need_to_split;
  wire wrap_need_to_split_q;
  wire wrap_need_to_split_q_i_2_n_0;
  wire wrap_need_to_split_q_i_3_n_0;
  wire [7:0]wrap_rest_len;
  wire [7:0]wrap_rest_len0;
  wire \wrap_rest_len[1]_i_1_n_0 ;
  wire \wrap_rest_len[7]_i_2_n_0 ;
  wire [7:0]wrap_unaligned_len;
  wire [7:0]wrap_unaligned_len_q;
  wire [7:6]NLW_next_mi_addr0_carry__2_CO_UNCONNECTED;
  wire [7:7]NLW_next_mi_addr0_carry__2_O_UNCONNECTED;

  assign m_axi_wstrb_3_sn_1 = m_axi_wstrb_3_sp_1;
  FDRE \S_AXI_AADDR_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[0]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[10] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[10]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[11] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[11]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[12] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[12]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[13] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[13]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[14] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[14]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[15] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[15]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[16] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[16]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[17] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[17]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[18] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[18]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[19] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[19]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[1]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[20] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[20]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[20] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[21] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[21]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[21] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[22] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[22]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[22] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[23] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[23]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[23] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[24] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[24]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[25] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[25]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[26] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[26]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[27] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[27]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[27] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[28] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[28]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[28] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[29] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[29]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[29] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[2]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[30] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[30]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[30] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[31] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[31]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[32] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[32]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[32] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[33] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[33]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[33] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[34] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[34]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[34] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[35] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[35]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[35] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[36] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[36]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[36] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[37] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[37]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[37] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[38] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[38]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[38] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[39] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[39]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[39] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[3]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[4]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[5]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[6]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[7]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[8] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[8]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[9] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[9]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[9] ),
        .R(1'b0));
  FDRE \S_AXI_ABURST_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awburst[0]),
        .Q(S_AXI_ABURST_Q[0]),
        .R(1'b0));
  FDRE \S_AXI_ABURST_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awburst[1]),
        .Q(S_AXI_ABURST_Q[1]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awcache[0]),
        .Q(m_axi_awcache[0]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awcache[1]),
        .Q(m_axi_awcache[1]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awcache[2]),
        .Q(m_axi_awcache[2]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awcache[3]),
        .Q(m_axi_awcache[3]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[0]),
        .Q(S_AXI_AID_Q[0]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[10] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[10]),
        .Q(S_AXI_AID_Q[10]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[11] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[11]),
        .Q(S_AXI_AID_Q[11]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[12] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[12]),
        .Q(S_AXI_AID_Q[12]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[13] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[13]),
        .Q(S_AXI_AID_Q[13]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[14] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[14]),
        .Q(S_AXI_AID_Q[14]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[15] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[15]),
        .Q(S_AXI_AID_Q[15]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[1]),
        .Q(S_AXI_AID_Q[1]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[2]),
        .Q(S_AXI_AID_Q[2]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[3]),
        .Q(S_AXI_AID_Q[3]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[4]),
        .Q(S_AXI_AID_Q[4]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[5]),
        .Q(S_AXI_AID_Q[5]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[6]),
        .Q(S_AXI_AID_Q[6]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[7]),
        .Q(S_AXI_AID_Q[7]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[8] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[8]),
        .Q(S_AXI_AID_Q[8]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[9] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awid[9]),
        .Q(S_AXI_AID_Q[9]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[0]),
        .Q(p_0_in_0[0]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[1]),
        .Q(p_0_in_0[1]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[2]),
        .Q(p_0_in_0[2]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[3]),
        .Q(p_0_in_0[3]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[4]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[5]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[6]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlen[7]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \S_AXI_ALOCK_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awlock),
        .Q(S_AXI_ALOCK_Q),
        .R(1'b0));
  FDRE \S_AXI_APROT_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awprot[0]),
        .Q(m_axi_awprot[0]),
        .R(1'b0));
  FDRE \S_AXI_APROT_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awprot[1]),
        .Q(m_axi_awprot[1]),
        .R(1'b0));
  FDRE \S_AXI_APROT_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awprot[2]),
        .Q(m_axi_awprot[2]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awqos[0]),
        .Q(m_axi_awqos[0]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awqos[1]),
        .Q(m_axi_awqos[1]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awqos[2]),
        .Q(m_axi_awqos[2]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awqos[3]),
        .Q(m_axi_awqos[3]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h44F4FFF4)) 
    S_AXI_AREADY_I_i_1__0
       (.I0(areset_d[0]),
        .I1(areset_d[1]),
        .I2(S_AXI_AREADY_I_reg_1),
        .I3(S_AXI_AREADY_I_reg_2),
        .I4(s_axi_arvalid),
        .O(\areset_d_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    S_AXI_AREADY_I_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_86),
        .Q(S_AXI_AREADY_I_reg_0),
        .R(SR));
  FDRE \S_AXI_AREGION_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awregion[0]),
        .Q(m_axi_awregion[0]),
        .R(1'b0));
  FDRE \S_AXI_AREGION_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awregion[1]),
        .Q(m_axi_awregion[1]),
        .R(1'b0));
  FDRE \S_AXI_AREGION_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awregion[2]),
        .Q(m_axi_awregion[2]),
        .R(1'b0));
  FDRE \S_AXI_AREGION_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awregion[3]),
        .Q(m_axi_awregion[3]),
        .R(1'b0));
  FDRE \S_AXI_ASIZE_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awsize[0]),
        .Q(S_AXI_ASIZE_Q[0]),
        .R(1'b0));
  FDRE \S_AXI_ASIZE_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awsize[1]),
        .Q(S_AXI_ASIZE_Q[1]),
        .R(1'b0));
  FDRE \S_AXI_ASIZE_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awsize[2]),
        .Q(S_AXI_ASIZE_Q[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \USE_B_CHANNEL.cmd_b_depth[0]_i_1 
       (.I0(\USE_B_CHANNEL.cmd_b_depth_reg [0]),
        .O(\USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0 ));
  FDRE \USE_B_CHANNEL.cmd_b_depth_reg[0] 
       (.C(CLK),
        .CE(cmd_queue_n_36),
        .D(\USE_B_CHANNEL.cmd_b_depth[0]_i_1_n_0 ),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg [0]),
        .R(SR));
  FDRE \USE_B_CHANNEL.cmd_b_depth_reg[1] 
       (.C(CLK),
        .CE(cmd_queue_n_36),
        .D(cmd_queue_n_32),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg [1]),
        .R(SR));
  FDRE \USE_B_CHANNEL.cmd_b_depth_reg[2] 
       (.C(CLK),
        .CE(cmd_queue_n_36),
        .D(cmd_queue_n_31),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg [2]),
        .R(SR));
  FDRE \USE_B_CHANNEL.cmd_b_depth_reg[3] 
       (.C(CLK),
        .CE(cmd_queue_n_36),
        .D(cmd_queue_n_30),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg [3]),
        .R(SR));
  FDRE \USE_B_CHANNEL.cmd_b_depth_reg[4] 
       (.C(CLK),
        .CE(cmd_queue_n_36),
        .D(cmd_queue_n_29),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg [4]),
        .R(SR));
  FDRE \USE_B_CHANNEL.cmd_b_depth_reg[5] 
       (.C(CLK),
        .CE(cmd_queue_n_36),
        .D(cmd_queue_n_28),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg [5]),
        .R(SR));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \USE_B_CHANNEL.cmd_b_empty_i_i_2 
       (.I0(\USE_B_CHANNEL.cmd_b_depth_reg [5]),
        .I1(\USE_B_CHANNEL.cmd_b_depth_reg [4]),
        .I2(\USE_B_CHANNEL.cmd_b_depth_reg [2]),
        .I3(\USE_B_CHANNEL.cmd_b_depth_reg [3]),
        .I4(\USE_B_CHANNEL.cmd_b_depth_reg [1]),
        .I5(\USE_B_CHANNEL.cmd_b_depth_reg [0]),
        .O(\USE_B_CHANNEL.cmd_b_empty_i_i_2_n_0 ));
  FDSE #(
    .INIT(1'b0)) 
    \USE_B_CHANNEL.cmd_b_empty_i_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_37),
        .Q(cmd_b_empty),
        .S(SR));
  design_1_auto_ds_0_axi_data_fifo_v2_1_28_axic_fifo \USE_B_CHANNEL.cmd_b_queue 
       (.CLK(CLK),
        .Q(pushed_commands_reg),
        .SR(SR),
        .\USE_WRITE.wr_cmd_b_ready (\USE_WRITE.wr_cmd_b_ready ),
        .access_is_fix_q(access_is_fix_q),
        .access_is_fix_q_reg(\USE_B_CHANNEL.cmd_b_queue_n_10 ),
        .access_is_incr_q(access_is_incr_q),
        .access_is_incr_q_reg(\USE_B_CHANNEL.cmd_b_queue_n_9 ),
        .access_is_wrap_q(access_is_wrap_q),
        .din(cmd_split_i),
        .dout(dout),
        .empty(empty),
        .fix_need_to_split_q(fix_need_to_split_q),
        .full(\inst/full ),
        .\gpr1.dout_i_reg[1] ({\num_transactions_q_reg_n_0_[3] ,\num_transactions_q_reg_n_0_[2] ,\num_transactions_q_reg_n_0_[1] ,\num_transactions_q_reg_n_0_[0] }),
        .\gpr1.dout_i_reg[1]_0 (p_0_in_0),
        .incr_need_to_split_q(incr_need_to_split_q),
        .out(out),
        .\pushed_commands_reg[7] (\USE_B_CHANNEL.cmd_b_queue_n_11 ),
        .split_ongoing(split_ongoing),
        .wr_en(cmd_b_push),
        .wrap_need_to_split_q(wrap_need_to_split_q));
  FDRE #(
    .INIT(1'b0)) 
    access_fit_mi_side_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\split_addr_mask_q[2]_i_1_n_0 ),
        .Q(access_fit_mi_side_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT2 #(
    .INIT(4'h1)) 
    access_is_fix_q_i_1
       (.I0(s_axi_awburst[1]),
        .I1(s_axi_awburst[0]),
        .O(access_is_fix));
  FDRE #(
    .INIT(1'b0)) 
    access_is_fix_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(access_is_fix),
        .Q(access_is_fix_q),
        .R(SR));
  LUT2 #(
    .INIT(4'h2)) 
    access_is_incr_q_i_1
       (.I0(s_axi_awburst[0]),
        .I1(s_axi_awburst[1]),
        .O(access_is_incr));
  FDRE #(
    .INIT(1'b0)) 
    access_is_incr_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(access_is_incr),
        .Q(access_is_incr_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT2 #(
    .INIT(4'h2)) 
    access_is_wrap_q_i_1
       (.I0(s_axi_awburst[1]),
        .I1(s_axi_awburst[0]),
        .O(access_is_wrap));
  FDRE #(
    .INIT(1'b0)) 
    access_is_wrap_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(access_is_wrap),
        .Q(access_is_wrap_q),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    \areset_d_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(SR),
        .Q(areset_d[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \areset_d_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(areset_d[0]),
        .Q(areset_d[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    cmd_b_push_block_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_35),
        .Q(cmd_b_push_block),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \cmd_mask_q[0]_i_1 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awlen[0]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awsize[2]),
        .I4(cmd_mask_q),
        .O(\cmd_mask_q[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFEFFFEEE)) 
    \cmd_mask_q[1]_i_1 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awlen[0]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[1]),
        .I5(cmd_mask_q),
        .O(\cmd_mask_q[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \cmd_mask_q[1]_i_2 
       (.I0(S_AXI_AREADY_I_reg_0),
        .I1(s_axi_awburst[0]),
        .I2(s_axi_awburst[1]),
        .O(cmd_mask_q));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \cmd_mask_q[2]_i_1 
       (.I0(s_axi_awburst[1]),
        .I1(s_axi_awburst[0]),
        .I2(\masked_addr_q[2]_i_2_n_0 ),
        .O(\cmd_mask_q[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \cmd_mask_q[3]_i_1 
       (.I0(s_axi_awburst[1]),
        .I1(s_axi_awburst[0]),
        .I2(\masked_addr_q[3]_i_2_n_0 ),
        .O(\cmd_mask_q[3]_i_1_n_0 ));
  FDRE \cmd_mask_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[0]_i_1_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[0] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[1]_i_1_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[1] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[2]_i_1_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[2] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[3]_i_1_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[3] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    cmd_push_block_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_38),
        .Q(cmd_push_block),
        .R(1'b0));
  design_1_auto_ds_0_axi_data_fifo_v2_1_28_axic_fifo__parameterized0__xdcDup__1 cmd_queue
       (.CLK(CLK),
        .D({cmd_queue_n_28,cmd_queue_n_29,cmd_queue_n_30,cmd_queue_n_31,cmd_queue_n_32}),
        .E(cmd_push),
        .Q(\USE_B_CHANNEL.cmd_b_depth_reg ),
        .SR(SR),
        .S_AXI_AREADY_I_reg(S_AXI_AREADY_I_reg_0),
        .S_AXI_AREADY_I_reg_0(areset_d[0]),
        .S_AXI_AREADY_I_reg_1(areset_d[1]),
        .\USE_B_CHANNEL.cmd_b_empty_i_reg (\USE_B_CHANNEL.cmd_b_empty_i_i_2_n_0 ),
        .\USE_WRITE.wr_cmd_b_ready (\USE_WRITE.wr_cmd_b_ready ),
        .access_fit_mi_side_q_reg(din),
        .access_is_fix_q(access_is_fix_q),
        .access_is_incr_q(access_is_incr_q),
        .access_is_wrap_q(access_is_wrap_q),
        .access_is_wrap_q_reg(cmd_queue_n_42),
        .\areset_d_reg[0] (cmd_queue_n_86),
        .cmd_b_empty(cmd_b_empty),
        .cmd_b_push_block(cmd_b_push_block),
        .cmd_b_push_block_reg(cmd_queue_n_35),
        .cmd_b_push_block_reg_0(cmd_queue_n_36),
        .cmd_b_push_block_reg_1(cmd_queue_n_37),
        .cmd_push_block(cmd_push_block),
        .cmd_push_block_reg(cmd_queue_n_38),
        .command_ongoing(command_ongoing),
        .command_ongoing_reg(command_ongoing_reg_0),
        .command_ongoing_reg_0(\USE_B_CHANNEL.cmd_b_queue_n_9 ),
        .\current_word_1_reg[1] (\current_word_1_reg[1] ),
        .\current_word_1_reg[1]_0 (\current_word_1_reg[1]_0 ),
        .\current_word_1_reg[2] (\current_word_1_reg[2] ),
        .\current_word_1_reg[3] (Q),
        .\current_word_1_reg[3]_0 (\current_word_1_reg[3] ),
        .din({cmd_split_i,access_fit_mi_side_q,\cmd_mask_q_reg_n_0_[3] ,\cmd_mask_q_reg_n_0_[2] ,\cmd_mask_q_reg_n_0_[1] ,\cmd_mask_q_reg_n_0_[0] ,S_AXI_ASIZE_Q}),
        .dout(\goreg_dm.dout_i_reg[28] ),
        .first_mi_word(first_mi_word),
        .fix_need_to_split_q(fix_need_to_split_q),
        .full(\inst/full ),
        .\goreg_dm.dout_i_reg[17] (D),
        .\gpr1.dout_i_reg[15] (\split_addr_mask_q_reg_n_0_[10] ),
        .\gpr1.dout_i_reg[15]_0 ({\split_addr_mask_q_reg_n_0_[3] ,\split_addr_mask_q_reg_n_0_[2] }),
        .\gpr1.dout_i_reg[15]_1 ({\S_AXI_AADDR_Q_reg_n_0_[3] ,\S_AXI_AADDR_Q_reg_n_0_[2] ,\S_AXI_AADDR_Q_reg_n_0_[1] ,\S_AXI_AADDR_Q_reg_n_0_[0] }),
        .\gpr1.dout_i_reg[15]_2 (\split_addr_mask_q_reg_n_0_[0] ),
        .\gpr1.dout_i_reg[15]_3 (\split_addr_mask_q_reg_n_0_[1] ),
        .incr_need_to_split_q(incr_need_to_split_q),
        .legal_wrap_len_q(legal_wrap_len_q),
        .\m_axi_awlen[4] (unalignment_addr_q),
        .\m_axi_awlen[4]_INST_0_i_3 (fix_len_q),
        .\m_axi_awlen[7] (wrap_unaligned_len_q),
        .\m_axi_awlen[7]_0 ({\S_AXI_ALEN_Q_reg_n_0_[7] ,\S_AXI_ALEN_Q_reg_n_0_[6] ,\S_AXI_ALEN_Q_reg_n_0_[5] ,\S_AXI_ALEN_Q_reg_n_0_[4] ,p_0_in_0}),
        .\m_axi_awlen[7]_INST_0_i_5 (\USE_B_CHANNEL.cmd_b_queue_n_10 ),
        .\m_axi_awlen[7]_INST_0_i_5_0 (\USE_B_CHANNEL.cmd_b_queue_n_11 ),
        .\m_axi_awlen[7]_INST_0_i_6 (wrap_rest_len),
        .\m_axi_awlen[7]_INST_0_i_6_0 (downsized_len_q),
        .m_axi_awready(m_axi_awready),
        .m_axi_awready_0(pushed_new_cmd),
        .m_axi_awvalid_INST_0_i_1(S_AXI_AID_Q),
        .m_axi_wdata(m_axi_wdata),
        .m_axi_wready(m_axi_wready),
        .m_axi_wstrb(m_axi_wstrb),
        .m_axi_wstrb_3_sp_1(m_axi_wstrb_3_sn_1),
        .m_axi_wvalid(m_axi_wvalid),
        .out(out),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_awvalid_0(cmd_queue_n_33),
        .s_axi_bid(s_axi_bid),
        .s_axi_wdata(s_axi_wdata),
        .s_axi_wready(s_axi_wready),
        .s_axi_wready_0(s_axi_wready_0),
        .s_axi_wstrb(s_axi_wstrb),
        .s_axi_wvalid(s_axi_wvalid),
        .s_axi_wvalid_0(E),
        .si_full_size_q(si_full_size_q),
        .split_ongoing(split_ongoing),
        .split_ongoing_reg(cmd_queue_n_41),
        .wr_en(cmd_b_push),
        .wrap_need_to_split_q(wrap_need_to_split_q));
  FDRE #(
    .INIT(1'b0)) 
    command_ongoing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_33),
        .Q(command_ongoing),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT4 #(
    .INIT(16'hFFEA)) 
    \downsized_len_q[0]_i_1 
       (.I0(s_axi_awlen[0]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awsize[2]),
        .O(\downsized_len_q[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT5 #(
    .INIT(32'h0222FEEE)) 
    \downsized_len_q[1]_i_1 
       (.I0(s_axi_awlen[1]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awsize[0]),
        .I4(\masked_addr_q[3]_i_2_n_0 ),
        .O(\downsized_len_q[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFEEEFEE2CEEECEE2)) 
    \downsized_len_q[2]_i_1 
       (.I0(s_axi_awlen[2]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[0]),
        .I5(\masked_addr_q[4]_i_2_n_0 ),
        .O(\downsized_len_q[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT5 #(
    .INIT(32'hFEEE0222)) 
    \downsized_len_q[3]_i_1 
       (.I0(s_axi_awlen[3]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awsize[0]),
        .I4(\masked_addr_q[5]_i_2_n_0 ),
        .O(\downsized_len_q[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8BB88BB88BB88)) 
    \downsized_len_q[4]_i_1 
       (.I0(\masked_addr_q[6]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(\num_transactions_q[0]_i_2_n_0 ),
        .I3(s_axi_awlen[4]),
        .I4(s_axi_awsize[1]),
        .I5(s_axi_awsize[0]),
        .O(\downsized_len_q[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8BB88BB88BB88)) 
    \downsized_len_q[5]_i_1 
       (.I0(\masked_addr_q[7]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(\masked_addr_q[7]_i_3_n_0 ),
        .I3(s_axi_awlen[5]),
        .I4(s_axi_awsize[1]),
        .I5(s_axi_awsize[0]),
        .O(\downsized_len_q[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT5 #(
    .INIT(32'hFEEE0222)) 
    \downsized_len_q[6]_i_1 
       (.I0(s_axi_awlen[6]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awsize[0]),
        .I4(\masked_addr_q[8]_i_2_n_0 ),
        .O(\downsized_len_q[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF55EA40BF15AA00)) 
    \downsized_len_q[7]_i_1 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[0]),
        .I3(\downsized_len_q[7]_i_2_n_0 ),
        .I4(s_axi_awlen[7]),
        .I5(s_axi_awlen[6]),
        .O(\downsized_len_q[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \downsized_len_q[7]_i_2 
       (.I0(s_axi_awlen[2]),
        .I1(s_axi_awlen[3]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[4]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[5]),
        .O(\downsized_len_q[7]_i_2_n_0 ));
  FDRE \downsized_len_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[0]_i_1_n_0 ),
        .Q(downsized_len_q[0]),
        .R(SR));
  FDRE \downsized_len_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[1]_i_1_n_0 ),
        .Q(downsized_len_q[1]),
        .R(SR));
  FDRE \downsized_len_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[2]_i_1_n_0 ),
        .Q(downsized_len_q[2]),
        .R(SR));
  FDRE \downsized_len_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[3]_i_1_n_0 ),
        .Q(downsized_len_q[3]),
        .R(SR));
  FDRE \downsized_len_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[4]_i_1_n_0 ),
        .Q(downsized_len_q[4]),
        .R(SR));
  FDRE \downsized_len_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[5]_i_1_n_0 ),
        .Q(downsized_len_q[5]),
        .R(SR));
  FDRE \downsized_len_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[6]_i_1_n_0 ),
        .Q(downsized_len_q[6]),
        .R(SR));
  FDRE \downsized_len_q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[7]_i_1_n_0 ),
        .Q(downsized_len_q[7]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \fix_len_q[0]_i_1 
       (.I0(s_axi_awsize[0]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[2]),
        .O(fix_len[0]));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \fix_len_q[2]_i_1 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[0]),
        .O(fix_len[2]));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \fix_len_q[3]_i_1 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awsize[2]),
        .O(fix_len[3]));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \fix_len_q[4]_i_1 
       (.I0(s_axi_awsize[0]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[1]),
        .O(fix_len[4]));
  FDRE \fix_len_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_len[0]),
        .Q(fix_len_q[0]),
        .R(SR));
  FDRE \fix_len_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awsize[2]),
        .Q(fix_len_q[1]),
        .R(SR));
  FDRE \fix_len_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_len[2]),
        .Q(fix_len_q[2]),
        .R(SR));
  FDRE \fix_len_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_len[3]),
        .Q(fix_len_q[3]),
        .R(SR));
  FDRE \fix_len_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_len[4]),
        .Q(fix_len_q[4]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT5 #(
    .INIT(32'h11111000)) 
    fix_need_to_split_q_i_1
       (.I0(s_axi_awburst[0]),
        .I1(s_axi_awburst[1]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awsize[1]),
        .I4(s_axi_awsize[2]),
        .O(fix_need_to_split));
  FDRE #(
    .INIT(1'b0)) 
    fix_need_to_split_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_need_to_split),
        .Q(fix_need_to_split_q),
        .R(SR));
  LUT6 #(
    .INIT(64'h4444444444444440)) 
    incr_need_to_split_q_i_1
       (.I0(s_axi_awburst[1]),
        .I1(s_axi_awburst[0]),
        .I2(num_transactions[3]),
        .I3(\num_transactions_q[2]_i_1_n_0 ),
        .I4(\num_transactions_q[1]_i_1_n_0 ),
        .I5(num_transactions[0]),
        .O(incr_need_to_split));
  FDRE #(
    .INIT(1'b0)) 
    incr_need_to_split_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(incr_need_to_split),
        .Q(incr_need_to_split_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT5 #(
    .INIT(32'h888A8A8A)) 
    legal_wrap_len_q_i_1
       (.I0(legal_wrap_len_q_i_2_n_0),
        .I1(legal_wrap_len_q_i_3_n_0),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[1]),
        .I4(s_axi_awsize[0]),
        .O(legal_wrap_len_q_i_1_n_0));
  LUT6 #(
    .INIT(64'h01011115FFFFFFFF)) 
    legal_wrap_len_q_i_2
       (.I0(s_axi_awlen[2]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awlen[0]),
        .I4(s_axi_awlen[1]),
        .I5(s_axi_awsize[2]),
        .O(legal_wrap_len_q_i_2_n_0));
  LUT5 #(
    .INIT(32'h00000001)) 
    legal_wrap_len_q_i_3
       (.I0(s_axi_awlen[5]),
        .I1(s_axi_awlen[7]),
        .I2(s_axi_awlen[6]),
        .I3(s_axi_awlen[4]),
        .I4(s_axi_awlen[3]),
        .O(legal_wrap_len_q_i_3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    legal_wrap_len_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(legal_wrap_len_q_i_1_n_0),
        .Q(legal_wrap_len_q),
        .R(SR));
  LUT5 #(
    .INIT(32'h00E2AAAA)) 
    \m_axi_awaddr[0]_INST_0 
       (.I0(\S_AXI_AADDR_Q_reg_n_0_[0] ),
        .I1(access_is_wrap_q),
        .I2(masked_addr_q[0]),
        .I3(access_is_incr_q),
        .I4(split_ongoing),
        .O(m_axi_awaddr[0]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[10]_INST_0 
       (.I0(next_mi_addr[10]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[10]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .O(m_axi_awaddr[10]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[11]_INST_0 
       (.I0(next_mi_addr[11]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[11]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[11] ),
        .O(m_axi_awaddr[11]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[12]_INST_0 
       (.I0(next_mi_addr[12]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[12]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .O(m_axi_awaddr[12]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[13]_INST_0 
       (.I0(next_mi_addr[13]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[13]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[13] ),
        .O(m_axi_awaddr[13]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[14]_INST_0 
       (.I0(next_mi_addr[14]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[14]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[14] ),
        .O(m_axi_awaddr[14]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[15]_INST_0 
       (.I0(next_mi_addr[15]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[15]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[15] ),
        .O(m_axi_awaddr[15]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[16]_INST_0 
       (.I0(next_mi_addr[16]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[16]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[16] ),
        .O(m_axi_awaddr[16]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[17]_INST_0 
       (.I0(next_mi_addr[17]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[17]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[17] ),
        .O(m_axi_awaddr[17]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[18]_INST_0 
       (.I0(next_mi_addr[18]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[18]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[18] ),
        .O(m_axi_awaddr[18]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[19]_INST_0 
       (.I0(next_mi_addr[19]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[19]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[19] ),
        .O(m_axi_awaddr[19]));
  LUT5 #(
    .INIT(32'h00E2AAAA)) 
    \m_axi_awaddr[1]_INST_0 
       (.I0(\S_AXI_AADDR_Q_reg_n_0_[1] ),
        .I1(access_is_wrap_q),
        .I2(masked_addr_q[1]),
        .I3(access_is_incr_q),
        .I4(split_ongoing),
        .O(m_axi_awaddr[1]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[20]_INST_0 
       (.I0(next_mi_addr[20]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[20]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[20] ),
        .O(m_axi_awaddr[20]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[21]_INST_0 
       (.I0(next_mi_addr[21]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[21]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[21] ),
        .O(m_axi_awaddr[21]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[22]_INST_0 
       (.I0(next_mi_addr[22]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[22]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[22] ),
        .O(m_axi_awaddr[22]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[23]_INST_0 
       (.I0(next_mi_addr[23]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[23]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[23] ),
        .O(m_axi_awaddr[23]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[24]_INST_0 
       (.I0(next_mi_addr[24]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[24]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[24] ),
        .O(m_axi_awaddr[24]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[25]_INST_0 
       (.I0(next_mi_addr[25]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[25]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[25] ),
        .O(m_axi_awaddr[25]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[26]_INST_0 
       (.I0(next_mi_addr[26]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[26]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[26] ),
        .O(m_axi_awaddr[26]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[27]_INST_0 
       (.I0(next_mi_addr[27]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[27]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[27] ),
        .O(m_axi_awaddr[27]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[28]_INST_0 
       (.I0(next_mi_addr[28]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[28]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[28] ),
        .O(m_axi_awaddr[28]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[29]_INST_0 
       (.I0(next_mi_addr[29]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[29]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[29] ),
        .O(m_axi_awaddr[29]));
  LUT6 #(
    .INIT(64'hFF00F0F0B8B8F0F0)) 
    \m_axi_awaddr[2]_INST_0 
       (.I0(masked_addr_q[2]),
        .I1(access_is_wrap_q),
        .I2(\S_AXI_AADDR_Q_reg_n_0_[2] ),
        .I3(next_mi_addr[2]),
        .I4(split_ongoing),
        .I5(access_is_incr_q),
        .O(m_axi_awaddr[2]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[30]_INST_0 
       (.I0(next_mi_addr[30]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[30]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[30] ),
        .O(m_axi_awaddr[30]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[31]_INST_0 
       (.I0(next_mi_addr[31]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[31]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[31] ),
        .O(m_axi_awaddr[31]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[32]_INST_0 
       (.I0(next_mi_addr[32]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[32]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[32] ),
        .O(m_axi_awaddr[32]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[33]_INST_0 
       (.I0(next_mi_addr[33]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[33]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[33] ),
        .O(m_axi_awaddr[33]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[34]_INST_0 
       (.I0(next_mi_addr[34]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[34]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[34] ),
        .O(m_axi_awaddr[34]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[35]_INST_0 
       (.I0(next_mi_addr[35]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[35]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[35] ),
        .O(m_axi_awaddr[35]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[36]_INST_0 
       (.I0(next_mi_addr[36]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[36]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[36] ),
        .O(m_axi_awaddr[36]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[37]_INST_0 
       (.I0(next_mi_addr[37]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[37]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[37] ),
        .O(m_axi_awaddr[37]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[38]_INST_0 
       (.I0(next_mi_addr[38]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[38]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[38] ),
        .O(m_axi_awaddr[38]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[39]_INST_0 
       (.I0(next_mi_addr[39]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[39]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[39] ),
        .O(m_axi_awaddr[39]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[3]_INST_0 
       (.I0(next_mi_addr[3]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[3]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[3] ),
        .O(m_axi_awaddr[3]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[4]_INST_0 
       (.I0(next_mi_addr[4]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[4]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[4] ),
        .O(m_axi_awaddr[4]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[5]_INST_0 
       (.I0(next_mi_addr[5]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[5]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[5] ),
        .O(m_axi_awaddr[5]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[6]_INST_0 
       (.I0(next_mi_addr[6]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[6]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[6] ),
        .O(m_axi_awaddr[6]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[7]_INST_0 
       (.I0(next_mi_addr[7]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[7]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[7] ),
        .O(m_axi_awaddr[7]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[8]_INST_0 
       (.I0(next_mi_addr[8]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[8]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[8] ),
        .O(m_axi_awaddr[8]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_awaddr[9]_INST_0 
       (.I0(next_mi_addr[9]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[9]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[9] ),
        .O(m_axi_awaddr[9]));
  LUT5 #(
    .INIT(32'hBABBBABA)) 
    \m_axi_awburst[0]_INST_0 
       (.I0(S_AXI_ABURST_Q[0]),
        .I1(access_fit_mi_side_q),
        .I2(access_is_fix_q),
        .I3(legal_wrap_len_q),
        .I4(access_is_wrap_q),
        .O(m_axi_awburst[0]));
  LUT5 #(
    .INIT(32'h8A888A8A)) 
    \m_axi_awburst[1]_INST_0 
       (.I0(S_AXI_ABURST_Q[1]),
        .I1(access_fit_mi_side_q),
        .I2(access_is_fix_q),
        .I3(legal_wrap_len_q),
        .I4(access_is_wrap_q),
        .O(m_axi_awburst[1]));
  LUT4 #(
    .INIT(16'h0002)) 
    \m_axi_awlock[0]_INST_0 
       (.I0(S_AXI_ALOCK_Q),
        .I1(incr_need_to_split_q),
        .I2(wrap_need_to_split_q),
        .I3(fix_need_to_split_q),
        .O(m_axi_awlock));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    \masked_addr_q[0]_i_1 
       (.I0(s_axi_awaddr[0]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awlen[0]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awsize[2]),
        .O(masked_addr[0]));
  LUT6 #(
    .INIT(64'h00002AAAAAAA2AAA)) 
    \masked_addr_q[10]_i_1 
       (.I0(s_axi_awaddr[10]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awlen[7]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awsize[2]),
        .I5(\num_transactions_q[0]_i_2_n_0 ),
        .O(masked_addr[10]));
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[11]_i_1 
       (.I0(s_axi_awaddr[11]),
        .I1(\num_transactions_q[1]_i_1_n_0 ),
        .O(masked_addr[11]));
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[12]_i_1 
       (.I0(s_axi_awaddr[12]),
        .I1(\num_transactions_q[2]_i_1_n_0 ),
        .O(masked_addr[12]));
  LUT6 #(
    .INIT(64'h202AAAAAAAAAAAAA)) 
    \masked_addr_q[13]_i_1 
       (.I0(s_axi_awaddr[13]),
        .I1(s_axi_awlen[6]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awlen[7]),
        .I4(s_axi_awsize[1]),
        .I5(s_axi_awsize[2]),
        .O(masked_addr[13]));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    \masked_addr_q[14]_i_1 
       (.I0(s_axi_awaddr[14]),
        .I1(s_axi_awlen[7]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awsize[1]),
        .I4(s_axi_awsize[2]),
        .O(masked_addr[14]));
  LUT6 #(
    .INIT(64'h0002000000020202)) 
    \masked_addr_q[1]_i_1 
       (.I0(s_axi_awaddr[1]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awlen[0]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[1]),
        .O(masked_addr[1]));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \masked_addr_q[2]_i_1 
       (.I0(s_axi_awaddr[2]),
        .I1(\masked_addr_q[2]_i_2_n_0 ),
        .O(masked_addr[2]));
  LUT6 #(
    .INIT(64'h0000015105050151)) 
    \masked_addr_q[2]_i_2 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awlen[2]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awlen[1]),
        .I4(s_axi_awsize[1]),
        .I5(s_axi_awlen[0]),
        .O(\masked_addr_q[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \masked_addr_q[3]_i_1 
       (.I0(s_axi_awaddr[3]),
        .I1(\masked_addr_q[3]_i_2_n_0 ),
        .O(masked_addr[3]));
  LUT6 #(
    .INIT(64'h0000015155550151)) 
    \masked_addr_q[3]_i_2 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awlen[3]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awlen[2]),
        .I4(s_axi_awsize[1]),
        .I5(\masked_addr_q[3]_i_3_n_0 ),
        .O(\masked_addr_q[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \masked_addr_q[3]_i_3 
       (.I0(s_axi_awlen[0]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awlen[1]),
        .O(\masked_addr_q[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h02020202020202A2)) 
    \masked_addr_q[4]_i_1 
       (.I0(s_axi_awaddr[4]),
        .I1(\masked_addr_q[4]_i_2_n_0 ),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[0]),
        .I5(s_axi_awsize[1]),
        .O(masked_addr[4]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[4]_i_2 
       (.I0(s_axi_awlen[1]),
        .I1(s_axi_awlen[2]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[3]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[4]),
        .O(\masked_addr_q[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[5]_i_1 
       (.I0(s_axi_awaddr[5]),
        .I1(\masked_addr_q[5]_i_2_n_0 ),
        .O(masked_addr[5]));
  LUT6 #(
    .INIT(64'hFEAEFFFFFEAE0000)) 
    \masked_addr_q[5]_i_2 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awlen[1]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awlen[0]),
        .I4(s_axi_awsize[2]),
        .I5(\downsized_len_q[7]_i_2_n_0 ),
        .O(\masked_addr_q[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT4 #(
    .INIT(16'h4700)) 
    \masked_addr_q[6]_i_1 
       (.I0(\masked_addr_q[6]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(\num_transactions_q[0]_i_2_n_0 ),
        .I3(s_axi_awaddr[6]),
        .O(masked_addr[6]));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT5 #(
    .INIT(32'hFCBBFC88)) 
    \masked_addr_q[6]_i_2 
       (.I0(s_axi_awlen[0]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awlen[1]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[2]),
        .O(\masked_addr_q[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT4 #(
    .INIT(16'h4700)) 
    \masked_addr_q[7]_i_1 
       (.I0(\masked_addr_q[7]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(\masked_addr_q[7]_i_3_n_0 ),
        .I3(s_axi_awaddr[7]),
        .O(masked_addr[7]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[7]_i_2 
       (.I0(s_axi_awlen[0]),
        .I1(s_axi_awlen[1]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[2]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[3]),
        .O(\masked_addr_q[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[7]_i_3 
       (.I0(s_axi_awlen[4]),
        .I1(s_axi_awlen[5]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[6]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[7]),
        .O(\masked_addr_q[7]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[8]_i_1 
       (.I0(s_axi_awaddr[8]),
        .I1(\masked_addr_q[8]_i_2_n_0 ),
        .O(masked_addr[8]));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \masked_addr_q[8]_i_2 
       (.I0(\masked_addr_q[4]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(\masked_addr_q[8]_i_3_n_0 ),
        .O(\masked_addr_q[8]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT5 #(
    .INIT(32'hAFA0C0C0)) 
    \masked_addr_q[8]_i_3 
       (.I0(s_axi_awlen[5]),
        .I1(s_axi_awlen[6]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[7]),
        .I4(s_axi_awsize[0]),
        .O(\masked_addr_q[8]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[9]_i_1 
       (.I0(s_axi_awaddr[9]),
        .I1(\masked_addr_q[9]_i_2_n_0 ),
        .O(masked_addr[9]));
  LUT6 #(
    .INIT(64'hBBB888B888888888)) 
    \masked_addr_q[9]_i_2 
       (.I0(\downsized_len_q[7]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awlen[7]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[6]),
        .I5(s_axi_awsize[1]),
        .O(\masked_addr_q[9]_i_2_n_0 ));
  FDRE \masked_addr_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[0]),
        .Q(masked_addr_q[0]),
        .R(SR));
  FDRE \masked_addr_q_reg[10] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[10]),
        .Q(masked_addr_q[10]),
        .R(SR));
  FDRE \masked_addr_q_reg[11] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[11]),
        .Q(masked_addr_q[11]),
        .R(SR));
  FDRE \masked_addr_q_reg[12] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[12]),
        .Q(masked_addr_q[12]),
        .R(SR));
  FDRE \masked_addr_q_reg[13] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[13]),
        .Q(masked_addr_q[13]),
        .R(SR));
  FDRE \masked_addr_q_reg[14] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[14]),
        .Q(masked_addr_q[14]),
        .R(SR));
  FDRE \masked_addr_q_reg[15] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[15]),
        .Q(masked_addr_q[15]),
        .R(SR));
  FDRE \masked_addr_q_reg[16] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[16]),
        .Q(masked_addr_q[16]),
        .R(SR));
  FDRE \masked_addr_q_reg[17] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[17]),
        .Q(masked_addr_q[17]),
        .R(SR));
  FDRE \masked_addr_q_reg[18] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[18]),
        .Q(masked_addr_q[18]),
        .R(SR));
  FDRE \masked_addr_q_reg[19] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[19]),
        .Q(masked_addr_q[19]),
        .R(SR));
  FDRE \masked_addr_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[1]),
        .Q(masked_addr_q[1]),
        .R(SR));
  FDRE \masked_addr_q_reg[20] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[20]),
        .Q(masked_addr_q[20]),
        .R(SR));
  FDRE \masked_addr_q_reg[21] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[21]),
        .Q(masked_addr_q[21]),
        .R(SR));
  FDRE \masked_addr_q_reg[22] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[22]),
        .Q(masked_addr_q[22]),
        .R(SR));
  FDRE \masked_addr_q_reg[23] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[23]),
        .Q(masked_addr_q[23]),
        .R(SR));
  FDRE \masked_addr_q_reg[24] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[24]),
        .Q(masked_addr_q[24]),
        .R(SR));
  FDRE \masked_addr_q_reg[25] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[25]),
        .Q(masked_addr_q[25]),
        .R(SR));
  FDRE \masked_addr_q_reg[26] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[26]),
        .Q(masked_addr_q[26]),
        .R(SR));
  FDRE \masked_addr_q_reg[27] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[27]),
        .Q(masked_addr_q[27]),
        .R(SR));
  FDRE \masked_addr_q_reg[28] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[28]),
        .Q(masked_addr_q[28]),
        .R(SR));
  FDRE \masked_addr_q_reg[29] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[29]),
        .Q(masked_addr_q[29]),
        .R(SR));
  FDRE \masked_addr_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[2]),
        .Q(masked_addr_q[2]),
        .R(SR));
  FDRE \masked_addr_q_reg[30] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[30]),
        .Q(masked_addr_q[30]),
        .R(SR));
  FDRE \masked_addr_q_reg[31] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[31]),
        .Q(masked_addr_q[31]),
        .R(SR));
  FDRE \masked_addr_q_reg[32] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[32]),
        .Q(masked_addr_q[32]),
        .R(SR));
  FDRE \masked_addr_q_reg[33] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[33]),
        .Q(masked_addr_q[33]),
        .R(SR));
  FDRE \masked_addr_q_reg[34] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[34]),
        .Q(masked_addr_q[34]),
        .R(SR));
  FDRE \masked_addr_q_reg[35] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[35]),
        .Q(masked_addr_q[35]),
        .R(SR));
  FDRE \masked_addr_q_reg[36] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[36]),
        .Q(masked_addr_q[36]),
        .R(SR));
  FDRE \masked_addr_q_reg[37] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[37]),
        .Q(masked_addr_q[37]),
        .R(SR));
  FDRE \masked_addr_q_reg[38] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[38]),
        .Q(masked_addr_q[38]),
        .R(SR));
  FDRE \masked_addr_q_reg[39] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_awaddr[39]),
        .Q(masked_addr_q[39]),
        .R(SR));
  FDRE \masked_addr_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[3]),
        .Q(masked_addr_q[3]),
        .R(SR));
  FDRE \masked_addr_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[4]),
        .Q(masked_addr_q[4]),
        .R(SR));
  FDRE \masked_addr_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[5]),
        .Q(masked_addr_q[5]),
        .R(SR));
  FDRE \masked_addr_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[6]),
        .Q(masked_addr_q[6]),
        .R(SR));
  FDRE \masked_addr_q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[7]),
        .Q(masked_addr_q[7]),
        .R(SR));
  FDRE \masked_addr_q_reg[8] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[8]),
        .Q(masked_addr_q[8]),
        .R(SR));
  FDRE \masked_addr_q_reg[9] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[9]),
        .Q(masked_addr_q[9]),
        .R(SR));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry_n_0,next_mi_addr0_carry_n_1,next_mi_addr0_carry_n_2,next_mi_addr0_carry_n_3,next_mi_addr0_carry_n_4,next_mi_addr0_carry_n_5,next_mi_addr0_carry_n_6,next_mi_addr0_carry_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,pre_mi_addr__0[10],1'b0}),
        .O({next_mi_addr0_carry_n_8,next_mi_addr0_carry_n_9,next_mi_addr0_carry_n_10,next_mi_addr0_carry_n_11,next_mi_addr0_carry_n_12,next_mi_addr0_carry_n_13,next_mi_addr0_carry_n_14,next_mi_addr0_carry_n_15}),
        .S({pre_mi_addr__0[16:11],next_mi_addr0_carry_i_8_n_0,pre_mi_addr__0[9]}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__0
       (.CI(next_mi_addr0_carry_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__0_n_0,next_mi_addr0_carry__0_n_1,next_mi_addr0_carry__0_n_2,next_mi_addr0_carry__0_n_3,next_mi_addr0_carry__0_n_4,next_mi_addr0_carry__0_n_5,next_mi_addr0_carry__0_n_6,next_mi_addr0_carry__0_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__0_n_8,next_mi_addr0_carry__0_n_9,next_mi_addr0_carry__0_n_10,next_mi_addr0_carry__0_n_11,next_mi_addr0_carry__0_n_12,next_mi_addr0_carry__0_n_13,next_mi_addr0_carry__0_n_14,next_mi_addr0_carry__0_n_15}),
        .S(pre_mi_addr__0[24:17]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_1
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[24] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[24]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[24]),
        .O(pre_mi_addr__0[24]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_2
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[23] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[23]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[23]),
        .O(pre_mi_addr__0[23]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_3
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[22] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[22]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[22]),
        .O(pre_mi_addr__0[22]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_4
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[21] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[21]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[21]),
        .O(pre_mi_addr__0[21]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_5
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[20] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[20]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[20]),
        .O(pre_mi_addr__0[20]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_6
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[19] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[19]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[19]),
        .O(pre_mi_addr__0[19]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_7
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[18] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[18]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[18]),
        .O(pre_mi_addr__0[18]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_8
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[17] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[17]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[17]),
        .O(pre_mi_addr__0[17]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__1
       (.CI(next_mi_addr0_carry__0_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__1_n_0,next_mi_addr0_carry__1_n_1,next_mi_addr0_carry__1_n_2,next_mi_addr0_carry__1_n_3,next_mi_addr0_carry__1_n_4,next_mi_addr0_carry__1_n_5,next_mi_addr0_carry__1_n_6,next_mi_addr0_carry__1_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__1_n_8,next_mi_addr0_carry__1_n_9,next_mi_addr0_carry__1_n_10,next_mi_addr0_carry__1_n_11,next_mi_addr0_carry__1_n_12,next_mi_addr0_carry__1_n_13,next_mi_addr0_carry__1_n_14,next_mi_addr0_carry__1_n_15}),
        .S(pre_mi_addr__0[32:25]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_1
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[32] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[32]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[32]),
        .O(pre_mi_addr__0[32]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_2
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[31] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[31]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[31]),
        .O(pre_mi_addr__0[31]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_3
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[30] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[30]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[30]),
        .O(pre_mi_addr__0[30]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_4
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[29] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[29]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[29]),
        .O(pre_mi_addr__0[29]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_5
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[28] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[28]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[28]),
        .O(pre_mi_addr__0[28]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_6
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[27] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[27]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[27]),
        .O(pre_mi_addr__0[27]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_7
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[26] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[26]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[26]),
        .O(pre_mi_addr__0[26]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_8
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[25] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[25]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[25]),
        .O(pre_mi_addr__0[25]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__2
       (.CI(next_mi_addr0_carry__1_n_0),
        .CI_TOP(1'b0),
        .CO({NLW_next_mi_addr0_carry__2_CO_UNCONNECTED[7:6],next_mi_addr0_carry__2_n_2,next_mi_addr0_carry__2_n_3,next_mi_addr0_carry__2_n_4,next_mi_addr0_carry__2_n_5,next_mi_addr0_carry__2_n_6,next_mi_addr0_carry__2_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({NLW_next_mi_addr0_carry__2_O_UNCONNECTED[7],next_mi_addr0_carry__2_n_9,next_mi_addr0_carry__2_n_10,next_mi_addr0_carry__2_n_11,next_mi_addr0_carry__2_n_12,next_mi_addr0_carry__2_n_13,next_mi_addr0_carry__2_n_14,next_mi_addr0_carry__2_n_15}),
        .S({1'b0,pre_mi_addr__0[39:33]}));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_1
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[39] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[39]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[39]),
        .O(pre_mi_addr__0[39]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_2
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[38] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[38]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[38]),
        .O(pre_mi_addr__0[38]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_3
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[37] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[37]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[37]),
        .O(pre_mi_addr__0[37]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_4
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[36] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[36]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[36]),
        .O(pre_mi_addr__0[36]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_5
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[35] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[35]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[35]),
        .O(pre_mi_addr__0[35]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_6
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[34] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[34]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[34]),
        .O(pre_mi_addr__0[34]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_7
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[33] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[33]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[33]),
        .O(pre_mi_addr__0[33]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_1
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[10]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[10]),
        .O(pre_mi_addr__0[10]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_2
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[16] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[16]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[16]),
        .O(pre_mi_addr__0[16]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_3
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[15] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[15]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[15]),
        .O(pre_mi_addr__0[15]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_4
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[14] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[14]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[14]),
        .O(pre_mi_addr__0[14]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_5
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[13] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[13]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[13]),
        .O(pre_mi_addr__0[13]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_6
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[12]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[12]),
        .O(pre_mi_addr__0[12]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_7
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[11] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[11]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[11]),
        .O(pre_mi_addr__0[11]));
  LUT6 #(
    .INIT(64'h47444777FFFFFFFF)) 
    next_mi_addr0_carry_i_8
       (.I0(next_mi_addr[10]),
        .I1(cmd_queue_n_41),
        .I2(masked_addr_q[10]),
        .I3(cmd_queue_n_42),
        .I4(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .I5(\split_addr_mask_q_reg_n_0_[10] ),
        .O(next_mi_addr0_carry_i_8_n_0));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_9
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[9] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[9]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[9]),
        .O(pre_mi_addr__0[9]));
  LUT6 #(
    .INIT(64'hA2A2A2808080A280)) 
    \next_mi_addr[2]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[2] ),
        .I1(cmd_queue_n_41),
        .I2(next_mi_addr[2]),
        .I3(\S_AXI_AADDR_Q_reg_n_0_[2] ),
        .I4(cmd_queue_n_42),
        .I5(masked_addr_q[2]),
        .O(pre_mi_addr[2]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[3]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[3] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[3] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[3]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[3]),
        .O(pre_mi_addr[3]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[4]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[4] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[4] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[4]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[4]),
        .O(pre_mi_addr[4]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[5]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[5] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[5] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[5]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[5]),
        .O(pre_mi_addr[5]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[6]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[6] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[6] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[6]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[6]),
        .O(pre_mi_addr[6]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[7]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[7] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[7]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[7]),
        .O(pre_mi_addr[7]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[8]_i_1 
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[8] ),
        .I2(cmd_queue_n_42),
        .I3(masked_addr_q[8]),
        .I4(cmd_queue_n_41),
        .I5(next_mi_addr[8]),
        .O(pre_mi_addr[8]));
  FDRE \next_mi_addr_reg[10] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_14),
        .Q(next_mi_addr[10]),
        .R(SR));
  FDRE \next_mi_addr_reg[11] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_13),
        .Q(next_mi_addr[11]),
        .R(SR));
  FDRE \next_mi_addr_reg[12] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_12),
        .Q(next_mi_addr[12]),
        .R(SR));
  FDRE \next_mi_addr_reg[13] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_11),
        .Q(next_mi_addr[13]),
        .R(SR));
  FDRE \next_mi_addr_reg[14] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_10),
        .Q(next_mi_addr[14]),
        .R(SR));
  FDRE \next_mi_addr_reg[15] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_9),
        .Q(next_mi_addr[15]),
        .R(SR));
  FDRE \next_mi_addr_reg[16] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_8),
        .Q(next_mi_addr[16]),
        .R(SR));
  FDRE \next_mi_addr_reg[17] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_15),
        .Q(next_mi_addr[17]),
        .R(SR));
  FDRE \next_mi_addr_reg[18] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_14),
        .Q(next_mi_addr[18]),
        .R(SR));
  FDRE \next_mi_addr_reg[19] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_13),
        .Q(next_mi_addr[19]),
        .R(SR));
  FDRE \next_mi_addr_reg[20] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_12),
        .Q(next_mi_addr[20]),
        .R(SR));
  FDRE \next_mi_addr_reg[21] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_11),
        .Q(next_mi_addr[21]),
        .R(SR));
  FDRE \next_mi_addr_reg[22] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_10),
        .Q(next_mi_addr[22]),
        .R(SR));
  FDRE \next_mi_addr_reg[23] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_9),
        .Q(next_mi_addr[23]),
        .R(SR));
  FDRE \next_mi_addr_reg[24] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_8),
        .Q(next_mi_addr[24]),
        .R(SR));
  FDRE \next_mi_addr_reg[25] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_15),
        .Q(next_mi_addr[25]),
        .R(SR));
  FDRE \next_mi_addr_reg[26] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_14),
        .Q(next_mi_addr[26]),
        .R(SR));
  FDRE \next_mi_addr_reg[27] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_13),
        .Q(next_mi_addr[27]),
        .R(SR));
  FDRE \next_mi_addr_reg[28] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_12),
        .Q(next_mi_addr[28]),
        .R(SR));
  FDRE \next_mi_addr_reg[29] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_11),
        .Q(next_mi_addr[29]),
        .R(SR));
  FDRE \next_mi_addr_reg[2] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[2]),
        .Q(next_mi_addr[2]),
        .R(SR));
  FDRE \next_mi_addr_reg[30] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_10),
        .Q(next_mi_addr[30]),
        .R(SR));
  FDRE \next_mi_addr_reg[31] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_9),
        .Q(next_mi_addr[31]),
        .R(SR));
  FDRE \next_mi_addr_reg[32] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_8),
        .Q(next_mi_addr[32]),
        .R(SR));
  FDRE \next_mi_addr_reg[33] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_15),
        .Q(next_mi_addr[33]),
        .R(SR));
  FDRE \next_mi_addr_reg[34] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_14),
        .Q(next_mi_addr[34]),
        .R(SR));
  FDRE \next_mi_addr_reg[35] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_13),
        .Q(next_mi_addr[35]),
        .R(SR));
  FDRE \next_mi_addr_reg[36] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_12),
        .Q(next_mi_addr[36]),
        .R(SR));
  FDRE \next_mi_addr_reg[37] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_11),
        .Q(next_mi_addr[37]),
        .R(SR));
  FDRE \next_mi_addr_reg[38] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_10),
        .Q(next_mi_addr[38]),
        .R(SR));
  FDRE \next_mi_addr_reg[39] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_9),
        .Q(next_mi_addr[39]),
        .R(SR));
  FDRE \next_mi_addr_reg[3] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[3]),
        .Q(next_mi_addr[3]),
        .R(SR));
  FDRE \next_mi_addr_reg[4] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[4]),
        .Q(next_mi_addr[4]),
        .R(SR));
  FDRE \next_mi_addr_reg[5] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[5]),
        .Q(next_mi_addr[5]),
        .R(SR));
  FDRE \next_mi_addr_reg[6] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[6]),
        .Q(next_mi_addr[6]),
        .R(SR));
  FDRE \next_mi_addr_reg[7] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[7]),
        .Q(next_mi_addr[7]),
        .R(SR));
  FDRE \next_mi_addr_reg[8] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[8]),
        .Q(next_mi_addr[8]),
        .R(SR));
  FDRE \next_mi_addr_reg[9] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_15),
        .Q(next_mi_addr[9]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT5 #(
    .INIT(32'hB8888888)) 
    \num_transactions_q[0]_i_1 
       (.I0(\num_transactions_q[0]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[0]),
        .I3(s_axi_awlen[7]),
        .I4(s_axi_awsize[1]),
        .O(num_transactions[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \num_transactions_q[0]_i_2 
       (.I0(s_axi_awlen[3]),
        .I1(s_axi_awlen[4]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[5]),
        .I4(s_axi_awsize[0]),
        .I5(s_axi_awlen[6]),
        .O(\num_transactions_q[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEEE222E200000000)) 
    \num_transactions_q[1]_i_1 
       (.I0(\num_transactions_q[1]_i_2_n_0 ),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awlen[5]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[4]),
        .I5(s_axi_awsize[2]),
        .O(\num_transactions_q[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \num_transactions_q[1]_i_2 
       (.I0(s_axi_awlen[6]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awlen[7]),
        .O(\num_transactions_q[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF8A8580800000000)) 
    \num_transactions_q[2]_i_1 
       (.I0(s_axi_awsize[0]),
        .I1(s_axi_awlen[7]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awlen[6]),
        .I4(s_axi_awlen[5]),
        .I5(s_axi_awsize[2]),
        .O(\num_transactions_q[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT5 #(
    .INIT(32'h88800080)) 
    \num_transactions_q[3]_i_1 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awlen[7]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[6]),
        .O(num_transactions[3]));
  FDRE \num_transactions_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(num_transactions[0]),
        .Q(\num_transactions_q_reg_n_0_[0] ),
        .R(SR));
  FDRE \num_transactions_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\num_transactions_q[1]_i_1_n_0 ),
        .Q(\num_transactions_q_reg_n_0_[1] ),
        .R(SR));
  FDRE \num_transactions_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\num_transactions_q[2]_i_1_n_0 ),
        .Q(\num_transactions_q_reg_n_0_[2] ),
        .R(SR));
  FDRE \num_transactions_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(num_transactions[3]),
        .Q(\num_transactions_q_reg_n_0_[3] ),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \pushed_commands[0]_i_1 
       (.I0(pushed_commands_reg[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \pushed_commands[1]_i_1 
       (.I0(pushed_commands_reg[0]),
        .I1(pushed_commands_reg[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \pushed_commands[2]_i_1 
       (.I0(pushed_commands_reg[2]),
        .I1(pushed_commands_reg[1]),
        .I2(pushed_commands_reg[0]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \pushed_commands[3]_i_1 
       (.I0(pushed_commands_reg[3]),
        .I1(pushed_commands_reg[0]),
        .I2(pushed_commands_reg[1]),
        .I3(pushed_commands_reg[2]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \pushed_commands[4]_i_1 
       (.I0(pushed_commands_reg[4]),
        .I1(pushed_commands_reg[2]),
        .I2(pushed_commands_reg[1]),
        .I3(pushed_commands_reg[0]),
        .I4(pushed_commands_reg[3]),
        .O(p_0_in[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \pushed_commands[5]_i_1 
       (.I0(pushed_commands_reg[5]),
        .I1(pushed_commands_reg[3]),
        .I2(pushed_commands_reg[0]),
        .I3(pushed_commands_reg[1]),
        .I4(pushed_commands_reg[2]),
        .I5(pushed_commands_reg[4]),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \pushed_commands[6]_i_1 
       (.I0(pushed_commands_reg[6]),
        .I1(\pushed_commands[7]_i_3_n_0 ),
        .O(p_0_in[6]));
  LUT2 #(
    .INIT(4'hB)) 
    \pushed_commands[7]_i_1 
       (.I0(S_AXI_AREADY_I_reg_0),
        .I1(out),
        .O(\pushed_commands[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \pushed_commands[7]_i_2 
       (.I0(pushed_commands_reg[7]),
        .I1(\pushed_commands[7]_i_3_n_0 ),
        .I2(pushed_commands_reg[6]),
        .O(p_0_in[7]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \pushed_commands[7]_i_3 
       (.I0(pushed_commands_reg[5]),
        .I1(pushed_commands_reg[3]),
        .I2(pushed_commands_reg[0]),
        .I3(pushed_commands_reg[1]),
        .I4(pushed_commands_reg[2]),
        .I5(pushed_commands_reg[4]),
        .O(\pushed_commands[7]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[0] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[0]),
        .Q(pushed_commands_reg[0]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[1] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[1]),
        .Q(pushed_commands_reg[1]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[2] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[2]),
        .Q(pushed_commands_reg[2]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[3] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[3]),
        .Q(pushed_commands_reg[3]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[4] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[4]),
        .Q(pushed_commands_reg[4]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[5] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[5]),
        .Q(pushed_commands_reg[5]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[6] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[6]),
        .Q(pushed_commands_reg[6]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[7] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in[7]),
        .Q(pushed_commands_reg[7]),
        .R(\pushed_commands[7]_i_1_n_0 ));
  FDRE \queue_id_reg[0] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[0]),
        .Q(s_axi_bid[0]),
        .R(SR));
  FDRE \queue_id_reg[10] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[10]),
        .Q(s_axi_bid[10]),
        .R(SR));
  FDRE \queue_id_reg[11] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[11]),
        .Q(s_axi_bid[11]),
        .R(SR));
  FDRE \queue_id_reg[12] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[12]),
        .Q(s_axi_bid[12]),
        .R(SR));
  FDRE \queue_id_reg[13] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[13]),
        .Q(s_axi_bid[13]),
        .R(SR));
  FDRE \queue_id_reg[14] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[14]),
        .Q(s_axi_bid[14]),
        .R(SR));
  FDRE \queue_id_reg[15] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[15]),
        .Q(s_axi_bid[15]),
        .R(SR));
  FDRE \queue_id_reg[1] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[1]),
        .Q(s_axi_bid[1]),
        .R(SR));
  FDRE \queue_id_reg[2] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[2]),
        .Q(s_axi_bid[2]),
        .R(SR));
  FDRE \queue_id_reg[3] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[3]),
        .Q(s_axi_bid[3]),
        .R(SR));
  FDRE \queue_id_reg[4] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[4]),
        .Q(s_axi_bid[4]),
        .R(SR));
  FDRE \queue_id_reg[5] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[5]),
        .Q(s_axi_bid[5]),
        .R(SR));
  FDRE \queue_id_reg[6] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[6]),
        .Q(s_axi_bid[6]),
        .R(SR));
  FDRE \queue_id_reg[7] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[7]),
        .Q(s_axi_bid[7]),
        .R(SR));
  FDRE \queue_id_reg[8] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[8]),
        .Q(s_axi_bid[8]),
        .R(SR));
  FDRE \queue_id_reg[9] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[9]),
        .Q(s_axi_bid[9]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT3 #(
    .INIT(8'h10)) 
    si_full_size_q_i_1
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awsize[2]),
        .O(si_full_size_q_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    si_full_size_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(si_full_size_q_i_1_n_0),
        .Q(si_full_size_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \split_addr_mask_q[0]_i_1 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awsize[2]),
        .O(split_addr_mask[0]));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \split_addr_mask_q[1]_i_1 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awsize[2]),
        .O(split_addr_mask[1]));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT3 #(
    .INIT(8'h15)) 
    \split_addr_mask_q[2]_i_1 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[0]),
        .O(\split_addr_mask_q[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \split_addr_mask_q[3]_i_1 
       (.I0(s_axi_awsize[2]),
        .O(split_addr_mask[3]));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT3 #(
    .INIT(8'h1F)) 
    \split_addr_mask_q[4]_i_1 
       (.I0(s_axi_awsize[0]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[2]),
        .O(split_addr_mask[4]));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \split_addr_mask_q[5]_i_1 
       (.I0(s_axi_awsize[2]),
        .I1(s_axi_awsize[1]),
        .O(split_addr_mask[5]));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \split_addr_mask_q[6]_i_1 
       (.I0(s_axi_awsize[1]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[0]),
        .O(split_addr_mask[6]));
  FDRE \split_addr_mask_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[0]),
        .Q(\split_addr_mask_q_reg_n_0_[0] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[10] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(1'b1),
        .Q(\split_addr_mask_q_reg_n_0_[10] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[1]),
        .Q(\split_addr_mask_q_reg_n_0_[1] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\split_addr_mask_q[2]_i_1_n_0 ),
        .Q(\split_addr_mask_q_reg_n_0_[2] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[3]),
        .Q(\split_addr_mask_q_reg_n_0_[3] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[4]),
        .Q(\split_addr_mask_q_reg_n_0_[4] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[5]),
        .Q(\split_addr_mask_q_reg_n_0_[5] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[6]),
        .Q(\split_addr_mask_q_reg_n_0_[6] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    split_ongoing_reg
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(cmd_split_i),
        .Q(split_ongoing),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT4 #(
    .INIT(16'hAA80)) 
    \unalignment_addr_q[0]_i_1 
       (.I0(s_axi_awaddr[2]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awsize[2]),
        .O(unalignment_addr[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \unalignment_addr_q[1]_i_1 
       (.I0(s_axi_awaddr[3]),
        .I1(s_axi_awsize[2]),
        .O(unalignment_addr[1]));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT4 #(
    .INIT(16'hA800)) 
    \unalignment_addr_q[2]_i_1 
       (.I0(s_axi_awaddr[4]),
        .I1(s_axi_awsize[0]),
        .I2(s_axi_awsize[1]),
        .I3(s_axi_awsize[2]),
        .O(unalignment_addr[2]));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \unalignment_addr_q[3]_i_1 
       (.I0(s_axi_awaddr[5]),
        .I1(s_axi_awsize[2]),
        .I2(s_axi_awsize[1]),
        .O(unalignment_addr[3]));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \unalignment_addr_q[4]_i_1 
       (.I0(s_axi_awaddr[6]),
        .I1(s_axi_awsize[1]),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[0]),
        .O(unalignment_addr[4]));
  FDRE \unalignment_addr_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[0]),
        .Q(unalignment_addr_q[0]),
        .R(SR));
  FDRE \unalignment_addr_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[1]),
        .Q(unalignment_addr_q[1]),
        .R(SR));
  FDRE \unalignment_addr_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[2]),
        .Q(unalignment_addr_q[2]),
        .R(SR));
  FDRE \unalignment_addr_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[3]),
        .Q(unalignment_addr_q[3]),
        .R(SR));
  FDRE \unalignment_addr_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[4]),
        .Q(unalignment_addr_q[4]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT5 #(
    .INIT(32'h000000E0)) 
    wrap_need_to_split_q_i_1
       (.I0(wrap_need_to_split_q_i_2_n_0),
        .I1(wrap_need_to_split_q_i_3_n_0),
        .I2(s_axi_awburst[1]),
        .I3(s_axi_awburst[0]),
        .I4(legal_wrap_len_q_i_1_n_0),
        .O(wrap_need_to_split));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    wrap_need_to_split_q_i_2
       (.I0(s_axi_awaddr[8]),
        .I1(\masked_addr_q[8]_i_2_n_0 ),
        .I2(s_axi_awaddr[9]),
        .I3(\masked_addr_q[9]_i_2_n_0 ),
        .I4(wrap_unaligned_len[4]),
        .I5(wrap_unaligned_len[5]),
        .O(wrap_need_to_split_q_i_2_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF22F2)) 
    wrap_need_to_split_q_i_3
       (.I0(s_axi_awaddr[2]),
        .I1(\masked_addr_q[2]_i_2_n_0 ),
        .I2(s_axi_awaddr[3]),
        .I3(\masked_addr_q[3]_i_2_n_0 ),
        .I4(wrap_unaligned_len[2]),
        .I5(wrap_unaligned_len[3]),
        .O(wrap_need_to_split_q_i_3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    wrap_need_to_split_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_need_to_split),
        .Q(wrap_need_to_split_q),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \wrap_rest_len[0]_i_1 
       (.I0(wrap_unaligned_len_q[0]),
        .O(wrap_rest_len0[0]));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wrap_rest_len[1]_i_1 
       (.I0(wrap_unaligned_len_q[0]),
        .I1(wrap_unaligned_len_q[1]),
        .O(\wrap_rest_len[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wrap_rest_len[2]_i_1 
       (.I0(wrap_unaligned_len_q[2]),
        .I1(wrap_unaligned_len_q[1]),
        .I2(wrap_unaligned_len_q[0]),
        .O(wrap_rest_len0[2]));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wrap_rest_len[3]_i_1 
       (.I0(wrap_unaligned_len_q[3]),
        .I1(wrap_unaligned_len_q[2]),
        .I2(wrap_unaligned_len_q[0]),
        .I3(wrap_unaligned_len_q[1]),
        .O(wrap_rest_len0[3]));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \wrap_rest_len[4]_i_1 
       (.I0(wrap_unaligned_len_q[4]),
        .I1(wrap_unaligned_len_q[3]),
        .I2(wrap_unaligned_len_q[1]),
        .I3(wrap_unaligned_len_q[0]),
        .I4(wrap_unaligned_len_q[2]),
        .O(wrap_rest_len0[4]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \wrap_rest_len[5]_i_1 
       (.I0(wrap_unaligned_len_q[5]),
        .I1(wrap_unaligned_len_q[4]),
        .I2(wrap_unaligned_len_q[2]),
        .I3(wrap_unaligned_len_q[0]),
        .I4(wrap_unaligned_len_q[1]),
        .I5(wrap_unaligned_len_q[3]),
        .O(wrap_rest_len0[5]));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wrap_rest_len[6]_i_1 
       (.I0(wrap_unaligned_len_q[6]),
        .I1(\wrap_rest_len[7]_i_2_n_0 ),
        .O(wrap_rest_len0[6]));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wrap_rest_len[7]_i_1 
       (.I0(wrap_unaligned_len_q[7]),
        .I1(wrap_unaligned_len_q[6]),
        .I2(\wrap_rest_len[7]_i_2_n_0 ),
        .O(wrap_rest_len0[7]));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \wrap_rest_len[7]_i_2 
       (.I0(wrap_unaligned_len_q[4]),
        .I1(wrap_unaligned_len_q[2]),
        .I2(wrap_unaligned_len_q[0]),
        .I3(wrap_unaligned_len_q[1]),
        .I4(wrap_unaligned_len_q[3]),
        .I5(wrap_unaligned_len_q[5]),
        .O(\wrap_rest_len[7]_i_2_n_0 ));
  FDRE \wrap_rest_len_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[0]),
        .Q(wrap_rest_len[0]),
        .R(SR));
  FDRE \wrap_rest_len_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrap_rest_len[1]_i_1_n_0 ),
        .Q(wrap_rest_len[1]),
        .R(SR));
  FDRE \wrap_rest_len_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[2]),
        .Q(wrap_rest_len[2]),
        .R(SR));
  FDRE \wrap_rest_len_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[3]),
        .Q(wrap_rest_len[3]),
        .R(SR));
  FDRE \wrap_rest_len_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[4]),
        .Q(wrap_rest_len[4]),
        .R(SR));
  FDRE \wrap_rest_len_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[5]),
        .Q(wrap_rest_len[5]),
        .R(SR));
  FDRE \wrap_rest_len_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[6]),
        .Q(wrap_rest_len[6]),
        .R(SR));
  FDRE \wrap_rest_len_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[7]),
        .Q(wrap_rest_len[7]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wrap_unaligned_len_q[0]_i_1 
       (.I0(s_axi_awaddr[2]),
        .I1(\masked_addr_q[2]_i_2_n_0 ),
        .O(wrap_unaligned_len[0]));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wrap_unaligned_len_q[1]_i_1 
       (.I0(s_axi_awaddr[3]),
        .I1(\masked_addr_q[3]_i_2_n_0 ),
        .O(wrap_unaligned_len[1]));
  LUT6 #(
    .INIT(64'hA8A8A8A8A8A8A808)) 
    \wrap_unaligned_len_q[2]_i_1 
       (.I0(s_axi_awaddr[4]),
        .I1(\masked_addr_q[4]_i_2_n_0 ),
        .I2(s_axi_awsize[2]),
        .I3(s_axi_awsize[0]),
        .I4(s_axi_awlen[0]),
        .I5(s_axi_awsize[1]),
        .O(wrap_unaligned_len[2]));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wrap_unaligned_len_q[3]_i_1 
       (.I0(s_axi_awaddr[5]),
        .I1(\masked_addr_q[5]_i_2_n_0 ),
        .O(wrap_unaligned_len[3]));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT4 #(
    .INIT(16'hB800)) 
    \wrap_unaligned_len_q[4]_i_1 
       (.I0(\masked_addr_q[6]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(\num_transactions_q[0]_i_2_n_0 ),
        .I3(s_axi_awaddr[6]),
        .O(wrap_unaligned_len[4]));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT4 #(
    .INIT(16'hB800)) 
    \wrap_unaligned_len_q[5]_i_1 
       (.I0(\masked_addr_q[7]_i_2_n_0 ),
        .I1(s_axi_awsize[2]),
        .I2(\masked_addr_q[7]_i_3_n_0 ),
        .I3(s_axi_awaddr[7]),
        .O(wrap_unaligned_len[5]));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wrap_unaligned_len_q[6]_i_1 
       (.I0(s_axi_awaddr[8]),
        .I1(\masked_addr_q[8]_i_2_n_0 ),
        .O(wrap_unaligned_len[6]));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wrap_unaligned_len_q[7]_i_1 
       (.I0(s_axi_awaddr[9]),
        .I1(\masked_addr_q[9]_i_2_n_0 ),
        .O(wrap_unaligned_len[7]));
  FDRE \wrap_unaligned_len_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[0]),
        .Q(wrap_unaligned_len_q[0]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[1]),
        .Q(wrap_unaligned_len_q[1]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[2]),
        .Q(wrap_unaligned_len_q[2]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[3]),
        .Q(wrap_unaligned_len_q[3]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[4]),
        .Q(wrap_unaligned_len_q[4]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[5]),
        .Q(wrap_unaligned_len_q[5]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[6]),
        .Q(wrap_unaligned_len_q[6]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[7]),
        .Q(wrap_unaligned_len_q[7]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_29_a_downsizer" *) 
module design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_a_downsizer__parameterized0
   (dout,
    access_fit_mi_side_q_reg_0,
    S_AXI_AREADY_I_reg_0,
    m_axi_arready_0,
    command_ongoing_reg_0,
    E,
    m_axi_rvalid_0,
    m_axi_rvalid_1,
    m_axi_rvalid_2,
    s_axi_rdata,
    s_axi_rid,
    m_axi_arlock,
    m_axi_araddr,
    s_axi_aresetn,
    s_axi_rvalid,
    m_axi_rvalid_3,
    m_axi_rready,
    D,
    \goreg_dm.dout_i_reg[2] ,
    m_axi_arburst,
    s_axi_rlast,
    m_axi_arcache,
    m_axi_arprot,
    m_axi_arregion,
    m_axi_arqos,
    CLK,
    SR,
    s_axi_arlock,
    S_AXI_AREADY_I_reg_1,
    s_axi_arsize,
    s_axi_arlen,
    s_axi_arburst,
    s_axi_arvalid,
    areset_d,
    m_axi_arready,
    out,
    s_axi_araddr,
    m_axi_rvalid,
    s_axi_rvalid_0,
    s_axi_rready,
    \WORD_LANE[3].S_AXI_RDATA_II_reg[127] ,
    m_axi_rdata,
    p_3_in,
    \S_AXI_RRESP_ACC_reg[0] ,
    \current_word_1_reg[1] ,
    \S_AXI_RRESP_ACC_reg[0]_0 ,
    \current_word_1_reg[2] ,
    \current_word_1_reg[1]_0 ,
    Q,
    first_mi_word,
    \current_word_1_reg[3] ,
    \s_axi_rdata[127]_INST_0_i_2 ,
    m_axi_rlast,
    s_axi_arid,
    s_axi_arcache,
    s_axi_arprot,
    s_axi_arregion,
    s_axi_arqos);
  output [19:0]dout;
  output [10:0]access_fit_mi_side_q_reg_0;
  output S_AXI_AREADY_I_reg_0;
  output m_axi_arready_0;
  output command_ongoing_reg_0;
  output [0:0]E;
  output [0:0]m_axi_rvalid_0;
  output [0:0]m_axi_rvalid_1;
  output [0:0]m_axi_rvalid_2;
  output [127:0]s_axi_rdata;
  output [15:0]s_axi_rid;
  output [0:0]m_axi_arlock;
  output [39:0]m_axi_araddr;
  output [0:0]s_axi_aresetn;
  output s_axi_rvalid;
  output [0:0]m_axi_rvalid_3;
  output m_axi_rready;
  output [3:0]D;
  output \goreg_dm.dout_i_reg[2] ;
  output [1:0]m_axi_arburst;
  output s_axi_rlast;
  output [3:0]m_axi_arcache;
  output [2:0]m_axi_arprot;
  output [3:0]m_axi_arregion;
  output [3:0]m_axi_arqos;
  input CLK;
  input [0:0]SR;
  input [0:0]s_axi_arlock;
  input S_AXI_AREADY_I_reg_1;
  input [2:0]s_axi_arsize;
  input [7:0]s_axi_arlen;
  input [1:0]s_axi_arburst;
  input s_axi_arvalid;
  input [1:0]areset_d;
  input m_axi_arready;
  input out;
  input [39:0]s_axi_araddr;
  input m_axi_rvalid;
  input s_axi_rvalid_0;
  input s_axi_rready;
  input \WORD_LANE[3].S_AXI_RDATA_II_reg[127] ;
  input [31:0]m_axi_rdata;
  input [127:0]p_3_in;
  input \S_AXI_RRESP_ACC_reg[0] ;
  input \current_word_1_reg[1] ;
  input \S_AXI_RRESP_ACC_reg[0]_0 ;
  input \current_word_1_reg[2] ;
  input \current_word_1_reg[1]_0 ;
  input [1:0]Q;
  input first_mi_word;
  input \current_word_1_reg[3] ;
  input \s_axi_rdata[127]_INST_0_i_2 ;
  input m_axi_rlast;
  input [15:0]s_axi_arid;
  input [3:0]s_axi_arcache;
  input [2:0]s_axi_arprot;
  input [3:0]s_axi_arregion;
  input [3:0]s_axi_arqos;

  wire CLK;
  wire [3:0]D;
  wire [0:0]E;
  wire [1:0]Q;
  wire [0:0]SR;
  wire \S_AXI_AADDR_Q_reg_n_0_[0] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[10] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[11] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[12] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[13] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[14] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[15] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[16] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[17] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[18] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[19] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[1] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[20] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[21] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[22] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[23] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[24] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[25] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[26] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[27] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[28] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[29] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[2] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[30] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[31] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[32] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[33] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[34] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[35] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[36] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[37] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[38] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[39] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[3] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[4] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[5] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[6] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[7] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[8] ;
  wire \S_AXI_AADDR_Q_reg_n_0_[9] ;
  wire [1:0]S_AXI_ABURST_Q;
  wire [15:0]S_AXI_AID_Q;
  wire \S_AXI_ALEN_Q_reg_n_0_[4] ;
  wire \S_AXI_ALEN_Q_reg_n_0_[5] ;
  wire \S_AXI_ALEN_Q_reg_n_0_[6] ;
  wire \S_AXI_ALEN_Q_reg_n_0_[7] ;
  wire [0:0]S_AXI_ALOCK_Q;
  wire S_AXI_AREADY_I_reg_0;
  wire S_AXI_AREADY_I_reg_1;
  wire [2:0]S_AXI_ASIZE_Q;
  wire \S_AXI_RRESP_ACC_reg[0] ;
  wire \S_AXI_RRESP_ACC_reg[0]_0 ;
  wire \WORD_LANE[3].S_AXI_RDATA_II_reg[127] ;
  wire access_fit_mi_side_q;
  wire [10:0]access_fit_mi_side_q_reg_0;
  wire access_is_fix;
  wire access_is_fix_q;
  wire access_is_incr;
  wire access_is_incr_q;
  wire access_is_wrap;
  wire access_is_wrap_q;
  wire [1:0]areset_d;
  wire \cmd_depth[0]_i_1_n_0 ;
  wire [5:0]cmd_depth_reg;
  wire cmd_empty;
  wire cmd_empty_i_2_n_0;
  wire cmd_mask_q;
  wire \cmd_mask_q[0]_i_1__0_n_0 ;
  wire \cmd_mask_q[1]_i_1__0_n_0 ;
  wire \cmd_mask_q[2]_i_1__0_n_0 ;
  wire \cmd_mask_q[3]_i_1__0_n_0 ;
  wire \cmd_mask_q_reg_n_0_[0] ;
  wire \cmd_mask_q_reg_n_0_[1] ;
  wire \cmd_mask_q_reg_n_0_[2] ;
  wire \cmd_mask_q_reg_n_0_[3] ;
  wire cmd_push;
  wire cmd_push_block;
  wire cmd_queue_n_177;
  wire cmd_queue_n_178;
  wire cmd_queue_n_33;
  wire cmd_queue_n_34;
  wire cmd_queue_n_35;
  wire cmd_queue_n_36;
  wire cmd_queue_n_37;
  wire cmd_queue_n_38;
  wire cmd_queue_n_41;
  wire cmd_queue_n_42;
  wire cmd_queue_n_43;
  wire cmd_split_i;
  wire command_ongoing;
  wire command_ongoing_reg_0;
  wire \current_word_1_reg[1] ;
  wire \current_word_1_reg[1]_0 ;
  wire \current_word_1_reg[2] ;
  wire \current_word_1_reg[3] ;
  wire [19:0]dout;
  wire [7:0]downsized_len_q;
  wire \downsized_len_q[0]_i_1__0_n_0 ;
  wire \downsized_len_q[1]_i_1__0_n_0 ;
  wire \downsized_len_q[2]_i_1__0_n_0 ;
  wire \downsized_len_q[3]_i_1__0_n_0 ;
  wire \downsized_len_q[4]_i_1__0_n_0 ;
  wire \downsized_len_q[5]_i_1__0_n_0 ;
  wire \downsized_len_q[6]_i_1__0_n_0 ;
  wire \downsized_len_q[7]_i_1__0_n_0 ;
  wire \downsized_len_q[7]_i_2__0_n_0 ;
  wire first_mi_word;
  wire [4:0]fix_len;
  wire [4:0]fix_len_q;
  wire fix_need_to_split;
  wire fix_need_to_split_q;
  wire \goreg_dm.dout_i_reg[2] ;
  wire incr_need_to_split;
  wire incr_need_to_split_q;
  wire legal_wrap_len_q;
  wire legal_wrap_len_q_i_1__0_n_0;
  wire legal_wrap_len_q_i_2__0_n_0;
  wire legal_wrap_len_q_i_3__0_n_0;
  wire [39:0]m_axi_araddr;
  wire [1:0]m_axi_arburst;
  wire [3:0]m_axi_arcache;
  wire [0:0]m_axi_arlock;
  wire [2:0]m_axi_arprot;
  wire [3:0]m_axi_arqos;
  wire m_axi_arready;
  wire m_axi_arready_0;
  wire [3:0]m_axi_arregion;
  wire [31:0]m_axi_rdata;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire m_axi_rvalid;
  wire [0:0]m_axi_rvalid_0;
  wire [0:0]m_axi_rvalid_1;
  wire [0:0]m_axi_rvalid_2;
  wire [0:0]m_axi_rvalid_3;
  wire [14:0]masked_addr;
  wire [39:0]masked_addr_q;
  wire \masked_addr_q[2]_i_2__0_n_0 ;
  wire \masked_addr_q[3]_i_2__0_n_0 ;
  wire \masked_addr_q[3]_i_3__0_n_0 ;
  wire \masked_addr_q[4]_i_2__0_n_0 ;
  wire \masked_addr_q[5]_i_2__0_n_0 ;
  wire \masked_addr_q[6]_i_2__0_n_0 ;
  wire \masked_addr_q[7]_i_2__0_n_0 ;
  wire \masked_addr_q[7]_i_3__0_n_0 ;
  wire \masked_addr_q[8]_i_2__0_n_0 ;
  wire \masked_addr_q[8]_i_3__0_n_0 ;
  wire \masked_addr_q[9]_i_2__0_n_0 ;
  wire [39:2]next_mi_addr;
  wire next_mi_addr0_carry__0_n_0;
  wire next_mi_addr0_carry__0_n_1;
  wire next_mi_addr0_carry__0_n_10;
  wire next_mi_addr0_carry__0_n_11;
  wire next_mi_addr0_carry__0_n_12;
  wire next_mi_addr0_carry__0_n_13;
  wire next_mi_addr0_carry__0_n_14;
  wire next_mi_addr0_carry__0_n_15;
  wire next_mi_addr0_carry__0_n_2;
  wire next_mi_addr0_carry__0_n_3;
  wire next_mi_addr0_carry__0_n_4;
  wire next_mi_addr0_carry__0_n_5;
  wire next_mi_addr0_carry__0_n_6;
  wire next_mi_addr0_carry__0_n_7;
  wire next_mi_addr0_carry__0_n_8;
  wire next_mi_addr0_carry__0_n_9;
  wire next_mi_addr0_carry__1_n_0;
  wire next_mi_addr0_carry__1_n_1;
  wire next_mi_addr0_carry__1_n_10;
  wire next_mi_addr0_carry__1_n_11;
  wire next_mi_addr0_carry__1_n_12;
  wire next_mi_addr0_carry__1_n_13;
  wire next_mi_addr0_carry__1_n_14;
  wire next_mi_addr0_carry__1_n_15;
  wire next_mi_addr0_carry__1_n_2;
  wire next_mi_addr0_carry__1_n_3;
  wire next_mi_addr0_carry__1_n_4;
  wire next_mi_addr0_carry__1_n_5;
  wire next_mi_addr0_carry__1_n_6;
  wire next_mi_addr0_carry__1_n_7;
  wire next_mi_addr0_carry__1_n_8;
  wire next_mi_addr0_carry__1_n_9;
  wire next_mi_addr0_carry__2_n_10;
  wire next_mi_addr0_carry__2_n_11;
  wire next_mi_addr0_carry__2_n_12;
  wire next_mi_addr0_carry__2_n_13;
  wire next_mi_addr0_carry__2_n_14;
  wire next_mi_addr0_carry__2_n_15;
  wire next_mi_addr0_carry__2_n_2;
  wire next_mi_addr0_carry__2_n_3;
  wire next_mi_addr0_carry__2_n_4;
  wire next_mi_addr0_carry__2_n_5;
  wire next_mi_addr0_carry__2_n_6;
  wire next_mi_addr0_carry__2_n_7;
  wire next_mi_addr0_carry__2_n_9;
  wire next_mi_addr0_carry_i_8__0_n_0;
  wire next_mi_addr0_carry_n_0;
  wire next_mi_addr0_carry_n_1;
  wire next_mi_addr0_carry_n_10;
  wire next_mi_addr0_carry_n_11;
  wire next_mi_addr0_carry_n_12;
  wire next_mi_addr0_carry_n_13;
  wire next_mi_addr0_carry_n_14;
  wire next_mi_addr0_carry_n_15;
  wire next_mi_addr0_carry_n_2;
  wire next_mi_addr0_carry_n_3;
  wire next_mi_addr0_carry_n_4;
  wire next_mi_addr0_carry_n_5;
  wire next_mi_addr0_carry_n_6;
  wire next_mi_addr0_carry_n_7;
  wire next_mi_addr0_carry_n_8;
  wire next_mi_addr0_carry_n_9;
  wire [3:0]num_transactions;
  wire [3:0]num_transactions_q;
  wire \num_transactions_q[0]_i_2__0_n_0 ;
  wire \num_transactions_q[1]_i_1__0_n_0 ;
  wire \num_transactions_q[1]_i_2__0_n_0 ;
  wire \num_transactions_q[2]_i_1__0_n_0 ;
  wire out;
  wire [3:0]p_0_in;
  wire [7:0]p_0_in__0;
  wire [127:0]p_3_in;
  wire [8:2]pre_mi_addr;
  wire [39:9]pre_mi_addr__0;
  wire \pushed_commands[7]_i_1__0_n_0 ;
  wire \pushed_commands[7]_i_3__0_n_0 ;
  wire [7:0]pushed_commands_reg;
  wire pushed_new_cmd;
  wire [39:0]s_axi_araddr;
  wire [1:0]s_axi_arburst;
  wire [3:0]s_axi_arcache;
  wire [0:0]s_axi_aresetn;
  wire [15:0]s_axi_arid;
  wire [7:0]s_axi_arlen;
  wire [0:0]s_axi_arlock;
  wire [2:0]s_axi_arprot;
  wire [3:0]s_axi_arqos;
  wire [3:0]s_axi_arregion;
  wire [2:0]s_axi_arsize;
  wire s_axi_arvalid;
  wire [127:0]s_axi_rdata;
  wire \s_axi_rdata[127]_INST_0_i_2 ;
  wire [15:0]s_axi_rid;
  wire s_axi_rlast;
  wire s_axi_rready;
  wire s_axi_rvalid;
  wire s_axi_rvalid_0;
  wire si_full_size_q;
  wire si_full_size_q_i_1__0_n_0;
  wire [6:0]split_addr_mask;
  wire \split_addr_mask_q[2]_i_1__0_n_0 ;
  wire \split_addr_mask_q_reg_n_0_[0] ;
  wire \split_addr_mask_q_reg_n_0_[10] ;
  wire \split_addr_mask_q_reg_n_0_[1] ;
  wire \split_addr_mask_q_reg_n_0_[2] ;
  wire \split_addr_mask_q_reg_n_0_[3] ;
  wire \split_addr_mask_q_reg_n_0_[4] ;
  wire \split_addr_mask_q_reg_n_0_[5] ;
  wire \split_addr_mask_q_reg_n_0_[6] ;
  wire split_ongoing;
  wire [4:0]unalignment_addr;
  wire [4:0]unalignment_addr_q;
  wire wrap_need_to_split;
  wire wrap_need_to_split_q;
  wire wrap_need_to_split_q_i_2__0_n_0;
  wire wrap_need_to_split_q_i_3__0_n_0;
  wire [7:0]wrap_rest_len;
  wire [7:0]wrap_rest_len0;
  wire \wrap_rest_len[1]_i_1__0_n_0 ;
  wire \wrap_rest_len[7]_i_2__0_n_0 ;
  wire [7:0]wrap_unaligned_len;
  wire [7:0]wrap_unaligned_len_q;
  wire [7:6]NLW_next_mi_addr0_carry__2_CO_UNCONNECTED;
  wire [7:7]NLW_next_mi_addr0_carry__2_O_UNCONNECTED;

  FDRE \S_AXI_AADDR_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[0]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[10] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[10]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[11] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[11]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[12] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[12]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[13] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[13]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[14] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[14]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[15] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[15]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[16] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[16]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[17] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[17]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[18] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[18]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[19] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[19]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[1]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[20] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[20]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[20] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[21] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[21]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[21] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[22] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[22]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[22] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[23] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[23]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[23] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[24] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[24]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[25] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[25]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[26] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[26]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[27] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[27]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[27] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[28] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[28]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[28] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[29] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[29]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[29] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[2]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[30] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[30]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[30] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[31] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[31]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[32] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[32]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[32] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[33] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[33]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[33] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[34] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[34]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[34] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[35] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[35]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[35] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[36] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[36]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[36] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[37] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[37]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[37] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[38] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[38]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[38] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[39] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[39]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[39] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[3]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[4]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[5]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[6]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[7]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[8] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[8]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \S_AXI_AADDR_Q_reg[9] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[9]),
        .Q(\S_AXI_AADDR_Q_reg_n_0_[9] ),
        .R(1'b0));
  FDRE \S_AXI_ABURST_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arburst[0]),
        .Q(S_AXI_ABURST_Q[0]),
        .R(1'b0));
  FDRE \S_AXI_ABURST_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arburst[1]),
        .Q(S_AXI_ABURST_Q[1]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arcache[0]),
        .Q(m_axi_arcache[0]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arcache[1]),
        .Q(m_axi_arcache[1]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arcache[2]),
        .Q(m_axi_arcache[2]),
        .R(1'b0));
  FDRE \S_AXI_ACACHE_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arcache[3]),
        .Q(m_axi_arcache[3]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[0]),
        .Q(S_AXI_AID_Q[0]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[10] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[10]),
        .Q(S_AXI_AID_Q[10]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[11] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[11]),
        .Q(S_AXI_AID_Q[11]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[12] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[12]),
        .Q(S_AXI_AID_Q[12]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[13] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[13]),
        .Q(S_AXI_AID_Q[13]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[14] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[14]),
        .Q(S_AXI_AID_Q[14]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[15] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[15]),
        .Q(S_AXI_AID_Q[15]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[1]),
        .Q(S_AXI_AID_Q[1]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[2]),
        .Q(S_AXI_AID_Q[2]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[3]),
        .Q(S_AXI_AID_Q[3]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[4]),
        .Q(S_AXI_AID_Q[4]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[5]),
        .Q(S_AXI_AID_Q[5]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[6]),
        .Q(S_AXI_AID_Q[6]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[7]),
        .Q(S_AXI_AID_Q[7]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[8] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[8]),
        .Q(S_AXI_AID_Q[8]),
        .R(1'b0));
  FDRE \S_AXI_AID_Q_reg[9] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arid[9]),
        .Q(S_AXI_AID_Q[9]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[0]),
        .Q(p_0_in[0]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[1]),
        .Q(p_0_in[1]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[2]),
        .Q(p_0_in[2]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[3]),
        .Q(p_0_in[3]),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[4]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[5]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[6]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \S_AXI_ALEN_Q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlen[7]),
        .Q(\S_AXI_ALEN_Q_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \S_AXI_ALOCK_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arlock),
        .Q(S_AXI_ALOCK_Q),
        .R(1'b0));
  FDRE \S_AXI_APROT_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arprot[0]),
        .Q(m_axi_arprot[0]),
        .R(1'b0));
  FDRE \S_AXI_APROT_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arprot[1]),
        .Q(m_axi_arprot[1]),
        .R(1'b0));
  FDRE \S_AXI_APROT_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arprot[2]),
        .Q(m_axi_arprot[2]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arqos[0]),
        .Q(m_axi_arqos[0]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arqos[1]),
        .Q(m_axi_arqos[1]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arqos[2]),
        .Q(m_axi_arqos[2]),
        .R(1'b0));
  FDRE \S_AXI_AQOS_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arqos[3]),
        .Q(m_axi_arqos[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    S_AXI_AREADY_I_reg
       (.C(CLK),
        .CE(1'b1),
        .D(S_AXI_AREADY_I_reg_1),
        .Q(S_AXI_AREADY_I_reg_0),
        .R(SR));
  FDRE \S_AXI_AREGION_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arregion[0]),
        .Q(m_axi_arregion[0]),
        .R(1'b0));
  FDRE \S_AXI_AREGION_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arregion[1]),
        .Q(m_axi_arregion[1]),
        .R(1'b0));
  FDRE \S_AXI_AREGION_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arregion[2]),
        .Q(m_axi_arregion[2]),
        .R(1'b0));
  FDRE \S_AXI_AREGION_Q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arregion[3]),
        .Q(m_axi_arregion[3]),
        .R(1'b0));
  FDRE \S_AXI_ASIZE_Q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arsize[0]),
        .Q(S_AXI_ASIZE_Q[0]),
        .R(1'b0));
  FDRE \S_AXI_ASIZE_Q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arsize[1]),
        .Q(S_AXI_ASIZE_Q[1]),
        .R(1'b0));
  FDRE \S_AXI_ASIZE_Q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arsize[2]),
        .Q(S_AXI_ASIZE_Q[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    access_fit_mi_side_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\split_addr_mask_q[2]_i_1__0_n_0 ),
        .Q(access_fit_mi_side_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT2 #(
    .INIT(4'h1)) 
    access_is_fix_q_i_1__0
       (.I0(s_axi_arburst[1]),
        .I1(s_axi_arburst[0]),
        .O(access_is_fix));
  FDRE #(
    .INIT(1'b0)) 
    access_is_fix_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(access_is_fix),
        .Q(access_is_fix_q),
        .R(SR));
  LUT2 #(
    .INIT(4'h2)) 
    access_is_incr_q_i_1__0
       (.I0(s_axi_arburst[0]),
        .I1(s_axi_arburst[1]),
        .O(access_is_incr));
  FDRE #(
    .INIT(1'b0)) 
    access_is_incr_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(access_is_incr),
        .Q(access_is_incr_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT2 #(
    .INIT(4'h2)) 
    access_is_wrap_q_i_1__0
       (.I0(s_axi_arburst[1]),
        .I1(s_axi_arburst[0]),
        .O(access_is_wrap));
  FDRE #(
    .INIT(1'b0)) 
    access_is_wrap_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(access_is_wrap),
        .Q(access_is_wrap_q),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_depth[0]_i_1 
       (.I0(cmd_depth_reg[0]),
        .O(\cmd_depth[0]_i_1_n_0 ));
  FDRE \cmd_depth_reg[0] 
       (.C(CLK),
        .CE(cmd_queue_n_42),
        .D(\cmd_depth[0]_i_1_n_0 ),
        .Q(cmd_depth_reg[0]),
        .R(SR));
  FDRE \cmd_depth_reg[1] 
       (.C(CLK),
        .CE(cmd_queue_n_42),
        .D(cmd_queue_n_37),
        .Q(cmd_depth_reg[1]),
        .R(SR));
  FDRE \cmd_depth_reg[2] 
       (.C(CLK),
        .CE(cmd_queue_n_42),
        .D(cmd_queue_n_36),
        .Q(cmd_depth_reg[2]),
        .R(SR));
  FDRE \cmd_depth_reg[3] 
       (.C(CLK),
        .CE(cmd_queue_n_42),
        .D(cmd_queue_n_35),
        .Q(cmd_depth_reg[3]),
        .R(SR));
  FDRE \cmd_depth_reg[4] 
       (.C(CLK),
        .CE(cmd_queue_n_42),
        .D(cmd_queue_n_34),
        .Q(cmd_depth_reg[4]),
        .R(SR));
  FDRE \cmd_depth_reg[5] 
       (.C(CLK),
        .CE(cmd_queue_n_42),
        .D(cmd_queue_n_33),
        .Q(cmd_depth_reg[5]),
        .R(SR));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    cmd_empty_i_2
       (.I0(cmd_depth_reg[5]),
        .I1(cmd_depth_reg[4]),
        .I2(cmd_depth_reg[2]),
        .I3(cmd_depth_reg[3]),
        .I4(cmd_depth_reg[1]),
        .I5(cmd_depth_reg[0]),
        .O(cmd_empty_i_2_n_0));
  FDSE #(
    .INIT(1'b0)) 
    cmd_empty_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_43),
        .Q(cmd_empty),
        .S(SR));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \cmd_mask_q[0]_i_1__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arlen[0]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arsize[2]),
        .I4(cmd_mask_q),
        .O(\cmd_mask_q[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFEFFFEEE)) 
    \cmd_mask_q[1]_i_1__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arlen[0]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[1]),
        .I5(cmd_mask_q),
        .O(\cmd_mask_q[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \cmd_mask_q[1]_i_2__0 
       (.I0(S_AXI_AREADY_I_reg_0),
        .I1(s_axi_arburst[0]),
        .I2(s_axi_arburst[1]),
        .O(cmd_mask_q));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \cmd_mask_q[2]_i_1__0 
       (.I0(s_axi_arburst[1]),
        .I1(s_axi_arburst[0]),
        .I2(\masked_addr_q[2]_i_2__0_n_0 ),
        .O(\cmd_mask_q[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \cmd_mask_q[3]_i_1__0 
       (.I0(s_axi_arburst[1]),
        .I1(s_axi_arburst[0]),
        .I2(\masked_addr_q[3]_i_2__0_n_0 ),
        .O(\cmd_mask_q[3]_i_1__0_n_0 ));
  FDRE \cmd_mask_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[0]_i_1__0_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[0] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[1]_i_1__0_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[1] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[2]_i_1__0_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[2] ),
        .R(SR));
  FDRE \cmd_mask_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\cmd_mask_q[3]_i_1__0_n_0 ),
        .Q(\cmd_mask_q_reg_n_0_[3] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    cmd_push_block_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_41),
        .Q(cmd_push_block),
        .R(1'b0));
  design_1_auto_ds_0_axi_data_fifo_v2_1_28_axic_fifo__parameterized0 cmd_queue
       (.CLK(CLK),
        .D({cmd_queue_n_33,cmd_queue_n_34,cmd_queue_n_35,cmd_queue_n_36,cmd_queue_n_37}),
        .E(cmd_push),
        .Q(cmd_depth_reg),
        .SR(SR),
        .\S_AXI_RRESP_ACC_reg[0] (\S_AXI_RRESP_ACC_reg[0] ),
        .\S_AXI_RRESP_ACC_reg[0]_0 (\S_AXI_RRESP_ACC_reg[0]_0 ),
        .\WORD_LANE[3].S_AXI_RDATA_II_reg[127] (\WORD_LANE[3].S_AXI_RDATA_II_reg[127] ),
        .access_fit_mi_side_q(access_fit_mi_side_q),
        .access_is_fix_q(access_is_fix_q),
        .access_is_incr_q(access_is_incr_q),
        .access_is_wrap_q(access_is_wrap_q),
        .access_is_wrap_q_reg(cmd_queue_n_178),
        .areset_d(areset_d),
        .cmd_empty(cmd_empty),
        .cmd_empty_reg(cmd_empty_i_2_n_0),
        .cmd_push_block(cmd_push_block),
        .cmd_push_block_reg(cmd_queue_n_41),
        .cmd_push_block_reg_0(cmd_queue_n_42),
        .cmd_push_block_reg_1(cmd_queue_n_43),
        .command_ongoing(command_ongoing),
        .command_ongoing_reg(command_ongoing_reg_0),
        .command_ongoing_reg_0(S_AXI_AREADY_I_reg_0),
        .\current_word_1_reg[1] (\current_word_1_reg[1] ),
        .\current_word_1_reg[1]_0 (\current_word_1_reg[1]_0 ),
        .\current_word_1_reg[2] (\current_word_1_reg[2] ),
        .\current_word_1_reg[3] (Q),
        .\current_word_1_reg[3]_0 (\current_word_1_reg[3] ),
        .din({cmd_split_i,access_fit_mi_side_q_reg_0}),
        .dout(dout),
        .first_mi_word(first_mi_word),
        .fix_need_to_split_q(fix_need_to_split_q),
        .\goreg_dm.dout_i_reg[17] (D),
        .\goreg_dm.dout_i_reg[2] (\goreg_dm.dout_i_reg[2] ),
        .\gpr1.dout_i_reg[15] ({\cmd_mask_q_reg_n_0_[3] ,\cmd_mask_q_reg_n_0_[2] ,\cmd_mask_q_reg_n_0_[1] ,\cmd_mask_q_reg_n_0_[0] ,S_AXI_ASIZE_Q}),
        .\gpr1.dout_i_reg[15]_0 (\split_addr_mask_q_reg_n_0_[10] ),
        .\gpr1.dout_i_reg[15]_1 ({\split_addr_mask_q_reg_n_0_[3] ,\split_addr_mask_q_reg_n_0_[2] }),
        .\gpr1.dout_i_reg[15]_2 ({\S_AXI_AADDR_Q_reg_n_0_[3] ,\S_AXI_AADDR_Q_reg_n_0_[2] ,\S_AXI_AADDR_Q_reg_n_0_[1] ,\S_AXI_AADDR_Q_reg_n_0_[0] }),
        .\gpr1.dout_i_reg[15]_3 (\split_addr_mask_q_reg_n_0_[0] ),
        .\gpr1.dout_i_reg[15]_4 (\split_addr_mask_q_reg_n_0_[1] ),
        .incr_need_to_split_q(incr_need_to_split_q),
        .legal_wrap_len_q(legal_wrap_len_q),
        .\m_axi_arlen[4] (unalignment_addr_q),
        .\m_axi_arlen[4]_INST_0_i_3 (fix_len_q),
        .\m_axi_arlen[7] (wrap_unaligned_len_q),
        .\m_axi_arlen[7]_0 ({\S_AXI_ALEN_Q_reg_n_0_[7] ,\S_AXI_ALEN_Q_reg_n_0_[6] ,\S_AXI_ALEN_Q_reg_n_0_[5] ,\S_AXI_ALEN_Q_reg_n_0_[4] ,p_0_in}),
        .\m_axi_arlen[7]_INST_0_i_1 (wrap_rest_len),
        .\m_axi_arlen[7]_INST_0_i_10 (pushed_commands_reg),
        .\m_axi_arlen[7]_INST_0_i_10_0 (num_transactions_q),
        .\m_axi_arlen[7]_INST_0_i_1_0 (downsized_len_q),
        .m_axi_arready(m_axi_arready),
        .m_axi_arready_0(m_axi_arready_0),
        .m_axi_arready_1(pushed_new_cmd),
        .m_axi_arvalid(S_AXI_AID_Q),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_rvalid_0(E),
        .m_axi_rvalid_1(m_axi_rvalid_0),
        .m_axi_rvalid_2(m_axi_rvalid_1),
        .m_axi_rvalid_3(m_axi_rvalid_2),
        .m_axi_rvalid_4(m_axi_rvalid_3),
        .out(out),
        .p_3_in(p_3_in),
        .s_axi_aresetn(s_axi_aresetn),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_arvalid_0(cmd_queue_n_38),
        .s_axi_rdata(s_axi_rdata),
        .\s_axi_rdata[127]_INST_0_i_2 (\s_axi_rdata[127]_INST_0_i_2 ),
        .s_axi_rid(s_axi_rid),
        .s_axi_rlast(s_axi_rlast),
        .s_axi_rready(s_axi_rready),
        .s_axi_rvalid(s_axi_rvalid),
        .s_axi_rvalid_0(s_axi_rvalid_0),
        .si_full_size_q(si_full_size_q),
        .split_ongoing(split_ongoing),
        .split_ongoing_reg(cmd_queue_n_177),
        .wrap_need_to_split_q(wrap_need_to_split_q));
  FDRE #(
    .INIT(1'b0)) 
    command_ongoing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cmd_queue_n_38),
        .Q(command_ongoing),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT4 #(
    .INIT(16'hFFEA)) 
    \downsized_len_q[0]_i_1__0 
       (.I0(s_axi_arlen[0]),
        .I1(s_axi_arsize[0]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arsize[2]),
        .O(\downsized_len_q[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT5 #(
    .INIT(32'h0222FEEE)) 
    \downsized_len_q[1]_i_1__0 
       (.I0(s_axi_arlen[1]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arsize[0]),
        .I4(\masked_addr_q[3]_i_2__0_n_0 ),
        .O(\downsized_len_q[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFEEEFEE2CEEECEE2)) 
    \downsized_len_q[2]_i_1__0 
       (.I0(s_axi_arlen[2]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[0]),
        .I5(\masked_addr_q[4]_i_2__0_n_0 ),
        .O(\downsized_len_q[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT5 #(
    .INIT(32'hFEEE0222)) 
    \downsized_len_q[3]_i_1__0 
       (.I0(s_axi_arlen[3]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arsize[0]),
        .I4(\masked_addr_q[5]_i_2__0_n_0 ),
        .O(\downsized_len_q[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8BB88BB88BB88)) 
    \downsized_len_q[4]_i_1__0 
       (.I0(\masked_addr_q[6]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\num_transactions_q[0]_i_2__0_n_0 ),
        .I3(s_axi_arlen[4]),
        .I4(s_axi_arsize[1]),
        .I5(s_axi_arsize[0]),
        .O(\downsized_len_q[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8BB88BB88BB88)) 
    \downsized_len_q[5]_i_1__0 
       (.I0(\masked_addr_q[7]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\masked_addr_q[7]_i_3__0_n_0 ),
        .I3(s_axi_arlen[5]),
        .I4(s_axi_arsize[1]),
        .I5(s_axi_arsize[0]),
        .O(\downsized_len_q[5]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT5 #(
    .INIT(32'hFEEE0222)) 
    \downsized_len_q[6]_i_1__0 
       (.I0(s_axi_arlen[6]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arsize[0]),
        .I4(\masked_addr_q[8]_i_2__0_n_0 ),
        .O(\downsized_len_q[6]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFF55EA40BF15AA00)) 
    \downsized_len_q[7]_i_1__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[0]),
        .I3(\downsized_len_q[7]_i_2__0_n_0 ),
        .I4(s_axi_arlen[7]),
        .I5(s_axi_arlen[6]),
        .O(\downsized_len_q[7]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \downsized_len_q[7]_i_2__0 
       (.I0(s_axi_arlen[2]),
        .I1(s_axi_arlen[3]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[4]),
        .I4(s_axi_arsize[0]),
        .I5(s_axi_arlen[5]),
        .O(\downsized_len_q[7]_i_2__0_n_0 ));
  FDRE \downsized_len_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[0]_i_1__0_n_0 ),
        .Q(downsized_len_q[0]),
        .R(SR));
  FDRE \downsized_len_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[1]_i_1__0_n_0 ),
        .Q(downsized_len_q[1]),
        .R(SR));
  FDRE \downsized_len_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[2]_i_1__0_n_0 ),
        .Q(downsized_len_q[2]),
        .R(SR));
  FDRE \downsized_len_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[3]_i_1__0_n_0 ),
        .Q(downsized_len_q[3]),
        .R(SR));
  FDRE \downsized_len_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[4]_i_1__0_n_0 ),
        .Q(downsized_len_q[4]),
        .R(SR));
  FDRE \downsized_len_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[5]_i_1__0_n_0 ),
        .Q(downsized_len_q[5]),
        .R(SR));
  FDRE \downsized_len_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[6]_i_1__0_n_0 ),
        .Q(downsized_len_q[6]),
        .R(SR));
  FDRE \downsized_len_q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\downsized_len_q[7]_i_1__0_n_0 ),
        .Q(downsized_len_q[7]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \fix_len_q[0]_i_1__0 
       (.I0(s_axi_arsize[0]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[2]),
        .O(fix_len[0]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \fix_len_q[2]_i_1__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[0]),
        .O(fix_len[2]));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \fix_len_q[3]_i_1__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arsize[2]),
        .O(fix_len[3]));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \fix_len_q[4]_i_1__0 
       (.I0(s_axi_arsize[0]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[1]),
        .O(fix_len[4]));
  FDRE \fix_len_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_len[0]),
        .Q(fix_len_q[0]),
        .R(SR));
  FDRE \fix_len_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_arsize[2]),
        .Q(fix_len_q[1]),
        .R(SR));
  FDRE \fix_len_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_len[2]),
        .Q(fix_len_q[2]),
        .R(SR));
  FDRE \fix_len_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_len[3]),
        .Q(fix_len_q[3]),
        .R(SR));
  FDRE \fix_len_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_len[4]),
        .Q(fix_len_q[4]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT5 #(
    .INIT(32'h11111000)) 
    fix_need_to_split_q_i_1__0
       (.I0(s_axi_arburst[0]),
        .I1(s_axi_arburst[1]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arsize[1]),
        .I4(s_axi_arsize[2]),
        .O(fix_need_to_split));
  FDRE #(
    .INIT(1'b0)) 
    fix_need_to_split_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(fix_need_to_split),
        .Q(fix_need_to_split_q),
        .R(SR));
  LUT6 #(
    .INIT(64'h4444444444444440)) 
    incr_need_to_split_q_i_1__0
       (.I0(s_axi_arburst[1]),
        .I1(s_axi_arburst[0]),
        .I2(num_transactions[3]),
        .I3(\num_transactions_q[2]_i_1__0_n_0 ),
        .I4(\num_transactions_q[1]_i_1__0_n_0 ),
        .I5(num_transactions[0]),
        .O(incr_need_to_split));
  FDRE #(
    .INIT(1'b0)) 
    incr_need_to_split_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(incr_need_to_split),
        .Q(incr_need_to_split_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT5 #(
    .INIT(32'h888A8A8A)) 
    legal_wrap_len_q_i_1__0
       (.I0(legal_wrap_len_q_i_2__0_n_0),
        .I1(legal_wrap_len_q_i_3__0_n_0),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arsize[1]),
        .I4(s_axi_arsize[0]),
        .O(legal_wrap_len_q_i_1__0_n_0));
  LUT6 #(
    .INIT(64'h01011115FFFFFFFF)) 
    legal_wrap_len_q_i_2__0
       (.I0(s_axi_arlen[2]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arlen[0]),
        .I4(s_axi_arlen[1]),
        .I5(s_axi_arsize[2]),
        .O(legal_wrap_len_q_i_2__0_n_0));
  LUT5 #(
    .INIT(32'h00000001)) 
    legal_wrap_len_q_i_3__0
       (.I0(s_axi_arlen[5]),
        .I1(s_axi_arlen[7]),
        .I2(s_axi_arlen[6]),
        .I3(s_axi_arlen[4]),
        .I4(s_axi_arlen[3]),
        .O(legal_wrap_len_q_i_3__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    legal_wrap_len_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(legal_wrap_len_q_i_1__0_n_0),
        .Q(legal_wrap_len_q),
        .R(SR));
  LUT5 #(
    .INIT(32'h00E2AAAA)) 
    \m_axi_araddr[0]_INST_0 
       (.I0(\S_AXI_AADDR_Q_reg_n_0_[0] ),
        .I1(access_is_wrap_q),
        .I2(masked_addr_q[0]),
        .I3(access_is_incr_q),
        .I4(split_ongoing),
        .O(m_axi_araddr[0]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[10]_INST_0 
       (.I0(next_mi_addr[10]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[10]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .O(m_axi_araddr[10]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[11]_INST_0 
       (.I0(next_mi_addr[11]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[11]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[11] ),
        .O(m_axi_araddr[11]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[12]_INST_0 
       (.I0(next_mi_addr[12]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[12]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .O(m_axi_araddr[12]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[13]_INST_0 
       (.I0(next_mi_addr[13]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[13]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[13] ),
        .O(m_axi_araddr[13]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[14]_INST_0 
       (.I0(next_mi_addr[14]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[14]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[14] ),
        .O(m_axi_araddr[14]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[15]_INST_0 
       (.I0(next_mi_addr[15]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[15]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[15] ),
        .O(m_axi_araddr[15]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[16]_INST_0 
       (.I0(next_mi_addr[16]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[16]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[16] ),
        .O(m_axi_araddr[16]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[17]_INST_0 
       (.I0(next_mi_addr[17]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[17]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[17] ),
        .O(m_axi_araddr[17]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[18]_INST_0 
       (.I0(next_mi_addr[18]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[18]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[18] ),
        .O(m_axi_araddr[18]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[19]_INST_0 
       (.I0(next_mi_addr[19]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[19]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[19] ),
        .O(m_axi_araddr[19]));
  LUT5 #(
    .INIT(32'h00E2AAAA)) 
    \m_axi_araddr[1]_INST_0 
       (.I0(\S_AXI_AADDR_Q_reg_n_0_[1] ),
        .I1(access_is_wrap_q),
        .I2(masked_addr_q[1]),
        .I3(access_is_incr_q),
        .I4(split_ongoing),
        .O(m_axi_araddr[1]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[20]_INST_0 
       (.I0(next_mi_addr[20]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[20]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[20] ),
        .O(m_axi_araddr[20]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[21]_INST_0 
       (.I0(next_mi_addr[21]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[21]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[21] ),
        .O(m_axi_araddr[21]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[22]_INST_0 
       (.I0(next_mi_addr[22]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[22]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[22] ),
        .O(m_axi_araddr[22]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[23]_INST_0 
       (.I0(next_mi_addr[23]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[23]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[23] ),
        .O(m_axi_araddr[23]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[24]_INST_0 
       (.I0(next_mi_addr[24]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[24]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[24] ),
        .O(m_axi_araddr[24]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[25]_INST_0 
       (.I0(next_mi_addr[25]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[25]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[25] ),
        .O(m_axi_araddr[25]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[26]_INST_0 
       (.I0(next_mi_addr[26]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[26]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[26] ),
        .O(m_axi_araddr[26]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[27]_INST_0 
       (.I0(next_mi_addr[27]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[27]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[27] ),
        .O(m_axi_araddr[27]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[28]_INST_0 
       (.I0(next_mi_addr[28]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[28]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[28] ),
        .O(m_axi_araddr[28]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[29]_INST_0 
       (.I0(next_mi_addr[29]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[29]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[29] ),
        .O(m_axi_araddr[29]));
  LUT6 #(
    .INIT(64'hFF00F0F0B8B8F0F0)) 
    \m_axi_araddr[2]_INST_0 
       (.I0(masked_addr_q[2]),
        .I1(access_is_wrap_q),
        .I2(\S_AXI_AADDR_Q_reg_n_0_[2] ),
        .I3(next_mi_addr[2]),
        .I4(split_ongoing),
        .I5(access_is_incr_q),
        .O(m_axi_araddr[2]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[30]_INST_0 
       (.I0(next_mi_addr[30]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[30]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[30] ),
        .O(m_axi_araddr[30]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[31]_INST_0 
       (.I0(next_mi_addr[31]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[31]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[31] ),
        .O(m_axi_araddr[31]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[32]_INST_0 
       (.I0(next_mi_addr[32]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[32]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[32] ),
        .O(m_axi_araddr[32]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[33]_INST_0 
       (.I0(next_mi_addr[33]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[33]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[33] ),
        .O(m_axi_araddr[33]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[34]_INST_0 
       (.I0(next_mi_addr[34]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[34]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[34] ),
        .O(m_axi_araddr[34]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[35]_INST_0 
       (.I0(next_mi_addr[35]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[35]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[35] ),
        .O(m_axi_araddr[35]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[36]_INST_0 
       (.I0(next_mi_addr[36]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[36]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[36] ),
        .O(m_axi_araddr[36]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[37]_INST_0 
       (.I0(next_mi_addr[37]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[37]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[37] ),
        .O(m_axi_araddr[37]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[38]_INST_0 
       (.I0(next_mi_addr[38]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[38]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[38] ),
        .O(m_axi_araddr[38]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[39]_INST_0 
       (.I0(next_mi_addr[39]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[39]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[39] ),
        .O(m_axi_araddr[39]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[3]_INST_0 
       (.I0(next_mi_addr[3]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[3]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[3] ),
        .O(m_axi_araddr[3]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[4]_INST_0 
       (.I0(next_mi_addr[4]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[4]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[4] ),
        .O(m_axi_araddr[4]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[5]_INST_0 
       (.I0(next_mi_addr[5]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[5]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[5] ),
        .O(m_axi_araddr[5]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[6]_INST_0 
       (.I0(next_mi_addr[6]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[6]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[6] ),
        .O(m_axi_araddr[6]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[7]_INST_0 
       (.I0(next_mi_addr[7]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[7]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[7] ),
        .O(m_axi_araddr[7]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[8]_INST_0 
       (.I0(next_mi_addr[8]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[8]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[8] ),
        .O(m_axi_araddr[8]));
  LUT6 #(
    .INIT(64'hBFB3BFBF8C808080)) 
    \m_axi_araddr[9]_INST_0 
       (.I0(next_mi_addr[9]),
        .I1(split_ongoing),
        .I2(access_is_incr_q),
        .I3(masked_addr_q[9]),
        .I4(access_is_wrap_q),
        .I5(\S_AXI_AADDR_Q_reg_n_0_[9] ),
        .O(m_axi_araddr[9]));
  LUT5 #(
    .INIT(32'hBABBBABA)) 
    \m_axi_arburst[0]_INST_0 
       (.I0(S_AXI_ABURST_Q[0]),
        .I1(access_fit_mi_side_q),
        .I2(access_is_fix_q),
        .I3(legal_wrap_len_q),
        .I4(access_is_wrap_q),
        .O(m_axi_arburst[0]));
  LUT5 #(
    .INIT(32'h8A888A8A)) 
    \m_axi_arburst[1]_INST_0 
       (.I0(S_AXI_ABURST_Q[1]),
        .I1(access_fit_mi_side_q),
        .I2(access_is_fix_q),
        .I3(legal_wrap_len_q),
        .I4(access_is_wrap_q),
        .O(m_axi_arburst[1]));
  LUT4 #(
    .INIT(16'h0002)) 
    \m_axi_arlock[0]_INST_0 
       (.I0(S_AXI_ALOCK_Q),
        .I1(incr_need_to_split_q),
        .I2(wrap_need_to_split_q),
        .I3(fix_need_to_split_q),
        .O(m_axi_arlock));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    \masked_addr_q[0]_i_1__0 
       (.I0(s_axi_araddr[0]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arlen[0]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arsize[2]),
        .O(masked_addr[0]));
  LUT6 #(
    .INIT(64'h00002AAAAAAA2AAA)) 
    \masked_addr_q[10]_i_1__0 
       (.I0(s_axi_araddr[10]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arlen[7]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arsize[2]),
        .I5(\num_transactions_q[0]_i_2__0_n_0 ),
        .O(masked_addr[10]));
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[11]_i_1__0 
       (.I0(s_axi_araddr[11]),
        .I1(\num_transactions_q[1]_i_1__0_n_0 ),
        .O(masked_addr[11]));
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[12]_i_1__0 
       (.I0(s_axi_araddr[12]),
        .I1(\num_transactions_q[2]_i_1__0_n_0 ),
        .O(masked_addr[12]));
  LUT6 #(
    .INIT(64'h202AAAAAAAAAAAAA)) 
    \masked_addr_q[13]_i_1__0 
       (.I0(s_axi_araddr[13]),
        .I1(s_axi_arlen[6]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arlen[7]),
        .I4(s_axi_arsize[1]),
        .I5(s_axi_arsize[2]),
        .O(masked_addr[13]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    \masked_addr_q[14]_i_1__0 
       (.I0(s_axi_araddr[14]),
        .I1(s_axi_arlen[7]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arsize[1]),
        .I4(s_axi_arsize[2]),
        .O(masked_addr[14]));
  LUT6 #(
    .INIT(64'h0002000000020202)) 
    \masked_addr_q[1]_i_1__0 
       (.I0(s_axi_araddr[1]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arlen[0]),
        .I4(s_axi_arsize[0]),
        .I5(s_axi_arlen[1]),
        .O(masked_addr[1]));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \masked_addr_q[2]_i_1__0 
       (.I0(s_axi_araddr[2]),
        .I1(\masked_addr_q[2]_i_2__0_n_0 ),
        .O(masked_addr[2]));
  LUT6 #(
    .INIT(64'h0000015105050151)) 
    \masked_addr_q[2]_i_2__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arlen[2]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arlen[1]),
        .I4(s_axi_arsize[1]),
        .I5(s_axi_arlen[0]),
        .O(\masked_addr_q[2]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \masked_addr_q[3]_i_1__0 
       (.I0(s_axi_araddr[3]),
        .I1(\masked_addr_q[3]_i_2__0_n_0 ),
        .O(masked_addr[3]));
  LUT6 #(
    .INIT(64'h0000015155550151)) 
    \masked_addr_q[3]_i_2__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arlen[3]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arlen[2]),
        .I4(s_axi_arsize[1]),
        .I5(\masked_addr_q[3]_i_3__0_n_0 ),
        .O(\masked_addr_q[3]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \masked_addr_q[3]_i_3__0 
       (.I0(s_axi_arlen[0]),
        .I1(s_axi_arsize[0]),
        .I2(s_axi_arlen[1]),
        .O(\masked_addr_q[3]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h02020202020202A2)) 
    \masked_addr_q[4]_i_1__0 
       (.I0(s_axi_araddr[4]),
        .I1(\masked_addr_q[4]_i_2__0_n_0 ),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[0]),
        .I5(s_axi_arsize[1]),
        .O(masked_addr[4]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[4]_i_2__0 
       (.I0(s_axi_arlen[1]),
        .I1(s_axi_arlen[2]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[3]),
        .I4(s_axi_arsize[0]),
        .I5(s_axi_arlen[4]),
        .O(\masked_addr_q[4]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[5]_i_1__0 
       (.I0(s_axi_araddr[5]),
        .I1(\masked_addr_q[5]_i_2__0_n_0 ),
        .O(masked_addr[5]));
  LUT6 #(
    .INIT(64'hFEAEFFFFFEAE0000)) 
    \masked_addr_q[5]_i_2__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arlen[1]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arlen[0]),
        .I4(s_axi_arsize[2]),
        .I5(\downsized_len_q[7]_i_2__0_n_0 ),
        .O(\masked_addr_q[5]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT4 #(
    .INIT(16'h4700)) 
    \masked_addr_q[6]_i_1__0 
       (.I0(\masked_addr_q[6]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\num_transactions_q[0]_i_2__0_n_0 ),
        .I3(s_axi_araddr[6]),
        .O(masked_addr[6]));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT5 #(
    .INIT(32'hFCBBFC88)) 
    \masked_addr_q[6]_i_2__0 
       (.I0(s_axi_arlen[0]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arlen[1]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[2]),
        .O(\masked_addr_q[6]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT4 #(
    .INIT(16'h4700)) 
    \masked_addr_q[7]_i_1__0 
       (.I0(\masked_addr_q[7]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\masked_addr_q[7]_i_3__0_n_0 ),
        .I3(s_axi_araddr[7]),
        .O(masked_addr[7]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[7]_i_2__0 
       (.I0(s_axi_arlen[0]),
        .I1(s_axi_arlen[1]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[2]),
        .I4(s_axi_arsize[0]),
        .I5(s_axi_arlen[3]),
        .O(\masked_addr_q[7]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \masked_addr_q[7]_i_3__0 
       (.I0(s_axi_arlen[4]),
        .I1(s_axi_arlen[5]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[6]),
        .I4(s_axi_arsize[0]),
        .I5(s_axi_arlen[7]),
        .O(\masked_addr_q[7]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[8]_i_1__0 
       (.I0(s_axi_araddr[8]),
        .I1(\masked_addr_q[8]_i_2__0_n_0 ),
        .O(masked_addr[8]));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \masked_addr_q[8]_i_2__0 
       (.I0(\masked_addr_q[4]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\masked_addr_q[8]_i_3__0_n_0 ),
        .O(\masked_addr_q[8]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT5 #(
    .INIT(32'hAFA0C0C0)) 
    \masked_addr_q[8]_i_3__0 
       (.I0(s_axi_arlen[5]),
        .I1(s_axi_arlen[6]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[7]),
        .I4(s_axi_arsize[0]),
        .O(\masked_addr_q[8]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \masked_addr_q[9]_i_1__0 
       (.I0(s_axi_araddr[9]),
        .I1(\masked_addr_q[9]_i_2__0_n_0 ),
        .O(masked_addr[9]));
  LUT6 #(
    .INIT(64'hBBB888B888888888)) 
    \masked_addr_q[9]_i_2__0 
       (.I0(\downsized_len_q[7]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arlen[7]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[6]),
        .I5(s_axi_arsize[1]),
        .O(\masked_addr_q[9]_i_2__0_n_0 ));
  FDRE \masked_addr_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[0]),
        .Q(masked_addr_q[0]),
        .R(SR));
  FDRE \masked_addr_q_reg[10] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[10]),
        .Q(masked_addr_q[10]),
        .R(SR));
  FDRE \masked_addr_q_reg[11] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[11]),
        .Q(masked_addr_q[11]),
        .R(SR));
  FDRE \masked_addr_q_reg[12] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[12]),
        .Q(masked_addr_q[12]),
        .R(SR));
  FDRE \masked_addr_q_reg[13] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[13]),
        .Q(masked_addr_q[13]),
        .R(SR));
  FDRE \masked_addr_q_reg[14] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[14]),
        .Q(masked_addr_q[14]),
        .R(SR));
  FDRE \masked_addr_q_reg[15] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[15]),
        .Q(masked_addr_q[15]),
        .R(SR));
  FDRE \masked_addr_q_reg[16] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[16]),
        .Q(masked_addr_q[16]),
        .R(SR));
  FDRE \masked_addr_q_reg[17] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[17]),
        .Q(masked_addr_q[17]),
        .R(SR));
  FDRE \masked_addr_q_reg[18] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[18]),
        .Q(masked_addr_q[18]),
        .R(SR));
  FDRE \masked_addr_q_reg[19] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[19]),
        .Q(masked_addr_q[19]),
        .R(SR));
  FDRE \masked_addr_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[1]),
        .Q(masked_addr_q[1]),
        .R(SR));
  FDRE \masked_addr_q_reg[20] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[20]),
        .Q(masked_addr_q[20]),
        .R(SR));
  FDRE \masked_addr_q_reg[21] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[21]),
        .Q(masked_addr_q[21]),
        .R(SR));
  FDRE \masked_addr_q_reg[22] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[22]),
        .Q(masked_addr_q[22]),
        .R(SR));
  FDRE \masked_addr_q_reg[23] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[23]),
        .Q(masked_addr_q[23]),
        .R(SR));
  FDRE \masked_addr_q_reg[24] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[24]),
        .Q(masked_addr_q[24]),
        .R(SR));
  FDRE \masked_addr_q_reg[25] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[25]),
        .Q(masked_addr_q[25]),
        .R(SR));
  FDRE \masked_addr_q_reg[26] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[26]),
        .Q(masked_addr_q[26]),
        .R(SR));
  FDRE \masked_addr_q_reg[27] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[27]),
        .Q(masked_addr_q[27]),
        .R(SR));
  FDRE \masked_addr_q_reg[28] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[28]),
        .Q(masked_addr_q[28]),
        .R(SR));
  FDRE \masked_addr_q_reg[29] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[29]),
        .Q(masked_addr_q[29]),
        .R(SR));
  FDRE \masked_addr_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[2]),
        .Q(masked_addr_q[2]),
        .R(SR));
  FDRE \masked_addr_q_reg[30] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[30]),
        .Q(masked_addr_q[30]),
        .R(SR));
  FDRE \masked_addr_q_reg[31] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[31]),
        .Q(masked_addr_q[31]),
        .R(SR));
  FDRE \masked_addr_q_reg[32] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[32]),
        .Q(masked_addr_q[32]),
        .R(SR));
  FDRE \masked_addr_q_reg[33] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[33]),
        .Q(masked_addr_q[33]),
        .R(SR));
  FDRE \masked_addr_q_reg[34] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[34]),
        .Q(masked_addr_q[34]),
        .R(SR));
  FDRE \masked_addr_q_reg[35] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[35]),
        .Q(masked_addr_q[35]),
        .R(SR));
  FDRE \masked_addr_q_reg[36] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[36]),
        .Q(masked_addr_q[36]),
        .R(SR));
  FDRE \masked_addr_q_reg[37] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[37]),
        .Q(masked_addr_q[37]),
        .R(SR));
  FDRE \masked_addr_q_reg[38] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[38]),
        .Q(masked_addr_q[38]),
        .R(SR));
  FDRE \masked_addr_q_reg[39] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(s_axi_araddr[39]),
        .Q(masked_addr_q[39]),
        .R(SR));
  FDRE \masked_addr_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[3]),
        .Q(masked_addr_q[3]),
        .R(SR));
  FDRE \masked_addr_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[4]),
        .Q(masked_addr_q[4]),
        .R(SR));
  FDRE \masked_addr_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[5]),
        .Q(masked_addr_q[5]),
        .R(SR));
  FDRE \masked_addr_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[6]),
        .Q(masked_addr_q[6]),
        .R(SR));
  FDRE \masked_addr_q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[7]),
        .Q(masked_addr_q[7]),
        .R(SR));
  FDRE \masked_addr_q_reg[8] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[8]),
        .Q(masked_addr_q[8]),
        .R(SR));
  FDRE \masked_addr_q_reg[9] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(masked_addr[9]),
        .Q(masked_addr_q[9]),
        .R(SR));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry_n_0,next_mi_addr0_carry_n_1,next_mi_addr0_carry_n_2,next_mi_addr0_carry_n_3,next_mi_addr0_carry_n_4,next_mi_addr0_carry_n_5,next_mi_addr0_carry_n_6,next_mi_addr0_carry_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,pre_mi_addr__0[10],1'b0}),
        .O({next_mi_addr0_carry_n_8,next_mi_addr0_carry_n_9,next_mi_addr0_carry_n_10,next_mi_addr0_carry_n_11,next_mi_addr0_carry_n_12,next_mi_addr0_carry_n_13,next_mi_addr0_carry_n_14,next_mi_addr0_carry_n_15}),
        .S({pre_mi_addr__0[16:11],next_mi_addr0_carry_i_8__0_n_0,pre_mi_addr__0[9]}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__0
       (.CI(next_mi_addr0_carry_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__0_n_0,next_mi_addr0_carry__0_n_1,next_mi_addr0_carry__0_n_2,next_mi_addr0_carry__0_n_3,next_mi_addr0_carry__0_n_4,next_mi_addr0_carry__0_n_5,next_mi_addr0_carry__0_n_6,next_mi_addr0_carry__0_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__0_n_8,next_mi_addr0_carry__0_n_9,next_mi_addr0_carry__0_n_10,next_mi_addr0_carry__0_n_11,next_mi_addr0_carry__0_n_12,next_mi_addr0_carry__0_n_13,next_mi_addr0_carry__0_n_14,next_mi_addr0_carry__0_n_15}),
        .S(pre_mi_addr__0[24:17]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_1__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[24] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[24]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[24]),
        .O(pre_mi_addr__0[24]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_2__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[23] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[23]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[23]),
        .O(pre_mi_addr__0[23]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_3__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[22] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[22]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[22]),
        .O(pre_mi_addr__0[22]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_4__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[21] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[21]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[21]),
        .O(pre_mi_addr__0[21]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_5__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[20] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[20]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[20]),
        .O(pre_mi_addr__0[20]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_6__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[19] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[19]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[19]),
        .O(pre_mi_addr__0[19]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_7__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[18] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[18]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[18]),
        .O(pre_mi_addr__0[18]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__0_i_8__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[17] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[17]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[17]),
        .O(pre_mi_addr__0[17]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__1
       (.CI(next_mi_addr0_carry__0_n_0),
        .CI_TOP(1'b0),
        .CO({next_mi_addr0_carry__1_n_0,next_mi_addr0_carry__1_n_1,next_mi_addr0_carry__1_n_2,next_mi_addr0_carry__1_n_3,next_mi_addr0_carry__1_n_4,next_mi_addr0_carry__1_n_5,next_mi_addr0_carry__1_n_6,next_mi_addr0_carry__1_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({next_mi_addr0_carry__1_n_8,next_mi_addr0_carry__1_n_9,next_mi_addr0_carry__1_n_10,next_mi_addr0_carry__1_n_11,next_mi_addr0_carry__1_n_12,next_mi_addr0_carry__1_n_13,next_mi_addr0_carry__1_n_14,next_mi_addr0_carry__1_n_15}),
        .S(pre_mi_addr__0[32:25]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_1__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[32] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[32]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[32]),
        .O(pre_mi_addr__0[32]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_2__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[31] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[31]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[31]),
        .O(pre_mi_addr__0[31]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_3__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[30] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[30]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[30]),
        .O(pre_mi_addr__0[30]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_4__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[29] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[29]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[29]),
        .O(pre_mi_addr__0[29]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_5__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[28] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[28]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[28]),
        .O(pre_mi_addr__0[28]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_6__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[27] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[27]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[27]),
        .O(pre_mi_addr__0[27]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_7__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[26] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[26]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[26]),
        .O(pre_mi_addr__0[26]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__1_i_8__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[25] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[25]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[25]),
        .O(pre_mi_addr__0[25]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 next_mi_addr0_carry__2
       (.CI(next_mi_addr0_carry__1_n_0),
        .CI_TOP(1'b0),
        .CO({NLW_next_mi_addr0_carry__2_CO_UNCONNECTED[7:6],next_mi_addr0_carry__2_n_2,next_mi_addr0_carry__2_n_3,next_mi_addr0_carry__2_n_4,next_mi_addr0_carry__2_n_5,next_mi_addr0_carry__2_n_6,next_mi_addr0_carry__2_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({NLW_next_mi_addr0_carry__2_O_UNCONNECTED[7],next_mi_addr0_carry__2_n_9,next_mi_addr0_carry__2_n_10,next_mi_addr0_carry__2_n_11,next_mi_addr0_carry__2_n_12,next_mi_addr0_carry__2_n_13,next_mi_addr0_carry__2_n_14,next_mi_addr0_carry__2_n_15}),
        .S({1'b0,pre_mi_addr__0[39:33]}));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_1__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[39] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[39]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[39]),
        .O(pre_mi_addr__0[39]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_2__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[38] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[38]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[38]),
        .O(pre_mi_addr__0[38]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_3__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[37] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[37]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[37]),
        .O(pre_mi_addr__0[37]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_4__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[36] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[36]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[36]),
        .O(pre_mi_addr__0[36]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_5__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[35] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[35]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[35]),
        .O(pre_mi_addr__0[35]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_6__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[34] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[34]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[34]),
        .O(pre_mi_addr__0[34]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry__2_i_7__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[33] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[33]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[33]),
        .O(pre_mi_addr__0[33]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_1__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[10]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[10]),
        .O(pre_mi_addr__0[10]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_2__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[16] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[16]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[16]),
        .O(pre_mi_addr__0[16]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_3__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[15] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[15]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[15]),
        .O(pre_mi_addr__0[15]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_4__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[14] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[14]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[14]),
        .O(pre_mi_addr__0[14]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_5__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[13] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[13]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[13]),
        .O(pre_mi_addr__0[13]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_6__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[12] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[12]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[12]),
        .O(pre_mi_addr__0[12]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_7__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[11] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[11]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[11]),
        .O(pre_mi_addr__0[11]));
  LUT6 #(
    .INIT(64'h47444777FFFFFFFF)) 
    next_mi_addr0_carry_i_8__0
       (.I0(next_mi_addr[10]),
        .I1(cmd_queue_n_177),
        .I2(masked_addr_q[10]),
        .I3(cmd_queue_n_178),
        .I4(\S_AXI_AADDR_Q_reg_n_0_[10] ),
        .I5(\split_addr_mask_q_reg_n_0_[10] ),
        .O(next_mi_addr0_carry_i_8__0_n_0));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    next_mi_addr0_carry_i_9__0
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[9] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[9]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[9]),
        .O(pre_mi_addr__0[9]));
  LUT6 #(
    .INIT(64'hA2A2A2808080A280)) 
    \next_mi_addr[2]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[2] ),
        .I1(cmd_queue_n_177),
        .I2(next_mi_addr[2]),
        .I3(\S_AXI_AADDR_Q_reg_n_0_[2] ),
        .I4(cmd_queue_n_178),
        .I5(masked_addr_q[2]),
        .O(pre_mi_addr[2]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[3]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[3] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[3] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[3]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[3]),
        .O(pre_mi_addr[3]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[4]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[4] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[4] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[4]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[4]),
        .O(pre_mi_addr[4]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[5]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[5] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[5] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[5]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[5]),
        .O(pre_mi_addr[5]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[6]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[6] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[6] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[6]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[6]),
        .O(pre_mi_addr[6]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[7]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[7] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[7]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[7]),
        .O(pre_mi_addr[7]));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \next_mi_addr[8]_i_1__0 
       (.I0(\split_addr_mask_q_reg_n_0_[10] ),
        .I1(\S_AXI_AADDR_Q_reg_n_0_[8] ),
        .I2(cmd_queue_n_178),
        .I3(masked_addr_q[8]),
        .I4(cmd_queue_n_177),
        .I5(next_mi_addr[8]),
        .O(pre_mi_addr[8]));
  FDRE \next_mi_addr_reg[10] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_14),
        .Q(next_mi_addr[10]),
        .R(SR));
  FDRE \next_mi_addr_reg[11] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_13),
        .Q(next_mi_addr[11]),
        .R(SR));
  FDRE \next_mi_addr_reg[12] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_12),
        .Q(next_mi_addr[12]),
        .R(SR));
  FDRE \next_mi_addr_reg[13] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_11),
        .Q(next_mi_addr[13]),
        .R(SR));
  FDRE \next_mi_addr_reg[14] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_10),
        .Q(next_mi_addr[14]),
        .R(SR));
  FDRE \next_mi_addr_reg[15] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_9),
        .Q(next_mi_addr[15]),
        .R(SR));
  FDRE \next_mi_addr_reg[16] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_8),
        .Q(next_mi_addr[16]),
        .R(SR));
  FDRE \next_mi_addr_reg[17] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_15),
        .Q(next_mi_addr[17]),
        .R(SR));
  FDRE \next_mi_addr_reg[18] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_14),
        .Q(next_mi_addr[18]),
        .R(SR));
  FDRE \next_mi_addr_reg[19] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_13),
        .Q(next_mi_addr[19]),
        .R(SR));
  FDRE \next_mi_addr_reg[20] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_12),
        .Q(next_mi_addr[20]),
        .R(SR));
  FDRE \next_mi_addr_reg[21] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_11),
        .Q(next_mi_addr[21]),
        .R(SR));
  FDRE \next_mi_addr_reg[22] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_10),
        .Q(next_mi_addr[22]),
        .R(SR));
  FDRE \next_mi_addr_reg[23] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_9),
        .Q(next_mi_addr[23]),
        .R(SR));
  FDRE \next_mi_addr_reg[24] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__0_n_8),
        .Q(next_mi_addr[24]),
        .R(SR));
  FDRE \next_mi_addr_reg[25] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_15),
        .Q(next_mi_addr[25]),
        .R(SR));
  FDRE \next_mi_addr_reg[26] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_14),
        .Q(next_mi_addr[26]),
        .R(SR));
  FDRE \next_mi_addr_reg[27] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_13),
        .Q(next_mi_addr[27]),
        .R(SR));
  FDRE \next_mi_addr_reg[28] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_12),
        .Q(next_mi_addr[28]),
        .R(SR));
  FDRE \next_mi_addr_reg[29] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_11),
        .Q(next_mi_addr[29]),
        .R(SR));
  FDRE \next_mi_addr_reg[2] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[2]),
        .Q(next_mi_addr[2]),
        .R(SR));
  FDRE \next_mi_addr_reg[30] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_10),
        .Q(next_mi_addr[30]),
        .R(SR));
  FDRE \next_mi_addr_reg[31] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_9),
        .Q(next_mi_addr[31]),
        .R(SR));
  FDRE \next_mi_addr_reg[32] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__1_n_8),
        .Q(next_mi_addr[32]),
        .R(SR));
  FDRE \next_mi_addr_reg[33] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_15),
        .Q(next_mi_addr[33]),
        .R(SR));
  FDRE \next_mi_addr_reg[34] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_14),
        .Q(next_mi_addr[34]),
        .R(SR));
  FDRE \next_mi_addr_reg[35] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_13),
        .Q(next_mi_addr[35]),
        .R(SR));
  FDRE \next_mi_addr_reg[36] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_12),
        .Q(next_mi_addr[36]),
        .R(SR));
  FDRE \next_mi_addr_reg[37] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_11),
        .Q(next_mi_addr[37]),
        .R(SR));
  FDRE \next_mi_addr_reg[38] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_10),
        .Q(next_mi_addr[38]),
        .R(SR));
  FDRE \next_mi_addr_reg[39] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry__2_n_9),
        .Q(next_mi_addr[39]),
        .R(SR));
  FDRE \next_mi_addr_reg[3] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[3]),
        .Q(next_mi_addr[3]),
        .R(SR));
  FDRE \next_mi_addr_reg[4] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[4]),
        .Q(next_mi_addr[4]),
        .R(SR));
  FDRE \next_mi_addr_reg[5] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[5]),
        .Q(next_mi_addr[5]),
        .R(SR));
  FDRE \next_mi_addr_reg[6] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[6]),
        .Q(next_mi_addr[6]),
        .R(SR));
  FDRE \next_mi_addr_reg[7] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[7]),
        .Q(next_mi_addr[7]),
        .R(SR));
  FDRE \next_mi_addr_reg[8] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(pre_mi_addr[8]),
        .Q(next_mi_addr[8]),
        .R(SR));
  FDRE \next_mi_addr_reg[9] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(next_mi_addr0_carry_n_15),
        .Q(next_mi_addr[9]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT5 #(
    .INIT(32'hB8888888)) 
    \num_transactions_q[0]_i_1__0 
       (.I0(\num_transactions_q[0]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[0]),
        .I3(s_axi_arlen[7]),
        .I4(s_axi_arsize[1]),
        .O(num_transactions[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \num_transactions_q[0]_i_2__0 
       (.I0(s_axi_arlen[3]),
        .I1(s_axi_arlen[4]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[5]),
        .I4(s_axi_arsize[0]),
        .I5(s_axi_arlen[6]),
        .O(\num_transactions_q[0]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hEEE222E200000000)) 
    \num_transactions_q[1]_i_1__0 
       (.I0(\num_transactions_q[1]_i_2__0_n_0 ),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arlen[5]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[4]),
        .I5(s_axi_arsize[2]),
        .O(\num_transactions_q[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \num_transactions_q[1]_i_2__0 
       (.I0(s_axi_arlen[6]),
        .I1(s_axi_arsize[0]),
        .I2(s_axi_arlen[7]),
        .O(\num_transactions_q[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hF8A8580800000000)) 
    \num_transactions_q[2]_i_1__0 
       (.I0(s_axi_arsize[0]),
        .I1(s_axi_arlen[7]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arlen[6]),
        .I4(s_axi_arlen[5]),
        .I5(s_axi_arsize[2]),
        .O(\num_transactions_q[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT5 #(
    .INIT(32'h88800080)) 
    \num_transactions_q[3]_i_1__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arlen[7]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[6]),
        .O(num_transactions[3]));
  FDRE \num_transactions_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(num_transactions[0]),
        .Q(num_transactions_q[0]),
        .R(SR));
  FDRE \num_transactions_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\num_transactions_q[1]_i_1__0_n_0 ),
        .Q(num_transactions_q[1]),
        .R(SR));
  FDRE \num_transactions_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\num_transactions_q[2]_i_1__0_n_0 ),
        .Q(num_transactions_q[2]),
        .R(SR));
  FDRE \num_transactions_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(num_transactions[3]),
        .Q(num_transactions_q[3]),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \pushed_commands[0]_i_1__0 
       (.I0(pushed_commands_reg[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \pushed_commands[1]_i_1__0 
       (.I0(pushed_commands_reg[0]),
        .I1(pushed_commands_reg[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \pushed_commands[2]_i_1__0 
       (.I0(pushed_commands_reg[2]),
        .I1(pushed_commands_reg[1]),
        .I2(pushed_commands_reg[0]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \pushed_commands[3]_i_1__0 
       (.I0(pushed_commands_reg[3]),
        .I1(pushed_commands_reg[0]),
        .I2(pushed_commands_reg[1]),
        .I3(pushed_commands_reg[2]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \pushed_commands[4]_i_1__0 
       (.I0(pushed_commands_reg[4]),
        .I1(pushed_commands_reg[2]),
        .I2(pushed_commands_reg[1]),
        .I3(pushed_commands_reg[0]),
        .I4(pushed_commands_reg[3]),
        .O(p_0_in__0[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \pushed_commands[5]_i_1__0 
       (.I0(pushed_commands_reg[5]),
        .I1(pushed_commands_reg[3]),
        .I2(pushed_commands_reg[0]),
        .I3(pushed_commands_reg[1]),
        .I4(pushed_commands_reg[2]),
        .I5(pushed_commands_reg[4]),
        .O(p_0_in__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \pushed_commands[6]_i_1__0 
       (.I0(pushed_commands_reg[6]),
        .I1(\pushed_commands[7]_i_3__0_n_0 ),
        .O(p_0_in__0[6]));
  LUT2 #(
    .INIT(4'hB)) 
    \pushed_commands[7]_i_1__0 
       (.I0(S_AXI_AREADY_I_reg_0),
        .I1(out),
        .O(\pushed_commands[7]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \pushed_commands[7]_i_2__0 
       (.I0(pushed_commands_reg[7]),
        .I1(\pushed_commands[7]_i_3__0_n_0 ),
        .I2(pushed_commands_reg[6]),
        .O(p_0_in__0[7]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \pushed_commands[7]_i_3__0 
       (.I0(pushed_commands_reg[5]),
        .I1(pushed_commands_reg[3]),
        .I2(pushed_commands_reg[0]),
        .I3(pushed_commands_reg[1]),
        .I4(pushed_commands_reg[2]),
        .I5(pushed_commands_reg[4]),
        .O(\pushed_commands[7]_i_3__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[0] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[0]),
        .Q(pushed_commands_reg[0]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[1] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[1]),
        .Q(pushed_commands_reg[1]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[2] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[2]),
        .Q(pushed_commands_reg[2]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[3] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[3]),
        .Q(pushed_commands_reg[3]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[4] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[4]),
        .Q(pushed_commands_reg[4]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[5] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[5]),
        .Q(pushed_commands_reg[5]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[6] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[6]),
        .Q(pushed_commands_reg[6]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \pushed_commands_reg[7] 
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(p_0_in__0[7]),
        .Q(pushed_commands_reg[7]),
        .R(\pushed_commands[7]_i_1__0_n_0 ));
  FDRE \queue_id_reg[0] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[0]),
        .Q(s_axi_rid[0]),
        .R(SR));
  FDRE \queue_id_reg[10] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[10]),
        .Q(s_axi_rid[10]),
        .R(SR));
  FDRE \queue_id_reg[11] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[11]),
        .Q(s_axi_rid[11]),
        .R(SR));
  FDRE \queue_id_reg[12] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[12]),
        .Q(s_axi_rid[12]),
        .R(SR));
  FDRE \queue_id_reg[13] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[13]),
        .Q(s_axi_rid[13]),
        .R(SR));
  FDRE \queue_id_reg[14] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[14]),
        .Q(s_axi_rid[14]),
        .R(SR));
  FDRE \queue_id_reg[15] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[15]),
        .Q(s_axi_rid[15]),
        .R(SR));
  FDRE \queue_id_reg[1] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[1]),
        .Q(s_axi_rid[1]),
        .R(SR));
  FDRE \queue_id_reg[2] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[2]),
        .Q(s_axi_rid[2]),
        .R(SR));
  FDRE \queue_id_reg[3] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[3]),
        .Q(s_axi_rid[3]),
        .R(SR));
  FDRE \queue_id_reg[4] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[4]),
        .Q(s_axi_rid[4]),
        .R(SR));
  FDRE \queue_id_reg[5] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[5]),
        .Q(s_axi_rid[5]),
        .R(SR));
  FDRE \queue_id_reg[6] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[6]),
        .Q(s_axi_rid[6]),
        .R(SR));
  FDRE \queue_id_reg[7] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[7]),
        .Q(s_axi_rid[7]),
        .R(SR));
  FDRE \queue_id_reg[8] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[8]),
        .Q(s_axi_rid[8]),
        .R(SR));
  FDRE \queue_id_reg[9] 
       (.C(CLK),
        .CE(cmd_push),
        .D(S_AXI_AID_Q[9]),
        .Q(s_axi_rid[9]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'h10)) 
    si_full_size_q_i_1__0
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arsize[0]),
        .I2(s_axi_arsize[2]),
        .O(si_full_size_q_i_1__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    si_full_size_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(si_full_size_q_i_1__0_n_0),
        .Q(si_full_size_q),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \split_addr_mask_q[0]_i_1__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arsize[0]),
        .I2(s_axi_arsize[2]),
        .O(split_addr_mask[0]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \split_addr_mask_q[1]_i_1__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arsize[2]),
        .O(split_addr_mask[1]));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'h15)) 
    \split_addr_mask_q[2]_i_1__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[0]),
        .O(\split_addr_mask_q[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \split_addr_mask_q[3]_i_1__0 
       (.I0(s_axi_arsize[2]),
        .O(split_addr_mask[3]));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'h1F)) 
    \split_addr_mask_q[4]_i_1__0 
       (.I0(s_axi_arsize[0]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[2]),
        .O(split_addr_mask[4]));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \split_addr_mask_q[5]_i_1__0 
       (.I0(s_axi_arsize[2]),
        .I1(s_axi_arsize[1]),
        .O(split_addr_mask[5]));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \split_addr_mask_q[6]_i_1__0 
       (.I0(s_axi_arsize[1]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[0]),
        .O(split_addr_mask[6]));
  FDRE \split_addr_mask_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[0]),
        .Q(\split_addr_mask_q_reg_n_0_[0] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[10] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(1'b1),
        .Q(\split_addr_mask_q_reg_n_0_[10] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[1]),
        .Q(\split_addr_mask_q_reg_n_0_[1] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(\split_addr_mask_q[2]_i_1__0_n_0 ),
        .Q(\split_addr_mask_q_reg_n_0_[2] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[3]),
        .Q(\split_addr_mask_q_reg_n_0_[3] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[4]),
        .Q(\split_addr_mask_q_reg_n_0_[4] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[5]),
        .Q(\split_addr_mask_q_reg_n_0_[5] ),
        .R(SR));
  FDRE \split_addr_mask_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(split_addr_mask[6]),
        .Q(\split_addr_mask_q_reg_n_0_[6] ),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    split_ongoing_reg
       (.C(CLK),
        .CE(pushed_new_cmd),
        .D(cmd_split_i),
        .Q(split_ongoing),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT4 #(
    .INIT(16'hAA80)) 
    \unalignment_addr_q[0]_i_1__0 
       (.I0(s_axi_araddr[2]),
        .I1(s_axi_arsize[0]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arsize[2]),
        .O(unalignment_addr[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \unalignment_addr_q[1]_i_1__0 
       (.I0(s_axi_araddr[3]),
        .I1(s_axi_arsize[2]),
        .O(unalignment_addr[1]));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT4 #(
    .INIT(16'hA800)) 
    \unalignment_addr_q[2]_i_1__0 
       (.I0(s_axi_araddr[4]),
        .I1(s_axi_arsize[0]),
        .I2(s_axi_arsize[1]),
        .I3(s_axi_arsize[2]),
        .O(unalignment_addr[2]));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \unalignment_addr_q[3]_i_1__0 
       (.I0(s_axi_araddr[5]),
        .I1(s_axi_arsize[2]),
        .I2(s_axi_arsize[1]),
        .O(unalignment_addr[3]));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \unalignment_addr_q[4]_i_1__0 
       (.I0(s_axi_araddr[6]),
        .I1(s_axi_arsize[1]),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arsize[0]),
        .O(unalignment_addr[4]));
  FDRE \unalignment_addr_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[0]),
        .Q(unalignment_addr_q[0]),
        .R(SR));
  FDRE \unalignment_addr_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[1]),
        .Q(unalignment_addr_q[1]),
        .R(SR));
  FDRE \unalignment_addr_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[2]),
        .Q(unalignment_addr_q[2]),
        .R(SR));
  FDRE \unalignment_addr_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[3]),
        .Q(unalignment_addr_q[3]),
        .R(SR));
  FDRE \unalignment_addr_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(unalignment_addr[4]),
        .Q(unalignment_addr_q[4]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT5 #(
    .INIT(32'h000000E0)) 
    wrap_need_to_split_q_i_1__0
       (.I0(wrap_need_to_split_q_i_2__0_n_0),
        .I1(wrap_need_to_split_q_i_3__0_n_0),
        .I2(s_axi_arburst[1]),
        .I3(s_axi_arburst[0]),
        .I4(legal_wrap_len_q_i_1__0_n_0),
        .O(wrap_need_to_split));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    wrap_need_to_split_q_i_2__0
       (.I0(s_axi_araddr[8]),
        .I1(\masked_addr_q[8]_i_2__0_n_0 ),
        .I2(s_axi_araddr[9]),
        .I3(\masked_addr_q[9]_i_2__0_n_0 ),
        .I4(wrap_unaligned_len[4]),
        .I5(wrap_unaligned_len[5]),
        .O(wrap_need_to_split_q_i_2__0_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF22F2)) 
    wrap_need_to_split_q_i_3__0
       (.I0(s_axi_araddr[2]),
        .I1(\masked_addr_q[2]_i_2__0_n_0 ),
        .I2(s_axi_araddr[3]),
        .I3(\masked_addr_q[3]_i_2__0_n_0 ),
        .I4(wrap_unaligned_len[2]),
        .I5(wrap_unaligned_len[3]),
        .O(wrap_need_to_split_q_i_3__0_n_0));
  FDRE #(
    .INIT(1'b0)) 
    wrap_need_to_split_q_reg
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_need_to_split),
        .Q(wrap_need_to_split_q),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \wrap_rest_len[0]_i_1__0 
       (.I0(wrap_unaligned_len_q[0]),
        .O(wrap_rest_len0[0]));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wrap_rest_len[1]_i_1__0 
       (.I0(wrap_unaligned_len_q[0]),
        .I1(wrap_unaligned_len_q[1]),
        .O(\wrap_rest_len[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wrap_rest_len[2]_i_1__0 
       (.I0(wrap_unaligned_len_q[2]),
        .I1(wrap_unaligned_len_q[1]),
        .I2(wrap_unaligned_len_q[0]),
        .O(wrap_rest_len0[2]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wrap_rest_len[3]_i_1__0 
       (.I0(wrap_unaligned_len_q[3]),
        .I1(wrap_unaligned_len_q[2]),
        .I2(wrap_unaligned_len_q[0]),
        .I3(wrap_unaligned_len_q[1]),
        .O(wrap_rest_len0[3]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \wrap_rest_len[4]_i_1__0 
       (.I0(wrap_unaligned_len_q[4]),
        .I1(wrap_unaligned_len_q[3]),
        .I2(wrap_unaligned_len_q[1]),
        .I3(wrap_unaligned_len_q[0]),
        .I4(wrap_unaligned_len_q[2]),
        .O(wrap_rest_len0[4]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \wrap_rest_len[5]_i_1__0 
       (.I0(wrap_unaligned_len_q[5]),
        .I1(wrap_unaligned_len_q[4]),
        .I2(wrap_unaligned_len_q[2]),
        .I3(wrap_unaligned_len_q[0]),
        .I4(wrap_unaligned_len_q[1]),
        .I5(wrap_unaligned_len_q[3]),
        .O(wrap_rest_len0[5]));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wrap_rest_len[6]_i_1__0 
       (.I0(wrap_unaligned_len_q[6]),
        .I1(\wrap_rest_len[7]_i_2__0_n_0 ),
        .O(wrap_rest_len0[6]));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \wrap_rest_len[7]_i_1__0 
       (.I0(wrap_unaligned_len_q[7]),
        .I1(wrap_unaligned_len_q[6]),
        .I2(\wrap_rest_len[7]_i_2__0_n_0 ),
        .O(wrap_rest_len0[7]));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \wrap_rest_len[7]_i_2__0 
       (.I0(wrap_unaligned_len_q[4]),
        .I1(wrap_unaligned_len_q[2]),
        .I2(wrap_unaligned_len_q[0]),
        .I3(wrap_unaligned_len_q[1]),
        .I4(wrap_unaligned_len_q[3]),
        .I5(wrap_unaligned_len_q[5]),
        .O(\wrap_rest_len[7]_i_2__0_n_0 ));
  FDRE \wrap_rest_len_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[0]),
        .Q(wrap_rest_len[0]),
        .R(SR));
  FDRE \wrap_rest_len_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrap_rest_len[1]_i_1__0_n_0 ),
        .Q(wrap_rest_len[1]),
        .R(SR));
  FDRE \wrap_rest_len_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[2]),
        .Q(wrap_rest_len[2]),
        .R(SR));
  FDRE \wrap_rest_len_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[3]),
        .Q(wrap_rest_len[3]),
        .R(SR));
  FDRE \wrap_rest_len_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[4]),
        .Q(wrap_rest_len[4]),
        .R(SR));
  FDRE \wrap_rest_len_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[5]),
        .Q(wrap_rest_len[5]),
        .R(SR));
  FDRE \wrap_rest_len_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[6]),
        .Q(wrap_rest_len[6]),
        .R(SR));
  FDRE \wrap_rest_len_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrap_rest_len0[7]),
        .Q(wrap_rest_len[7]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wrap_unaligned_len_q[0]_i_1__0 
       (.I0(s_axi_araddr[2]),
        .I1(\masked_addr_q[2]_i_2__0_n_0 ),
        .O(wrap_unaligned_len[0]));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wrap_unaligned_len_q[1]_i_1__0 
       (.I0(s_axi_araddr[3]),
        .I1(\masked_addr_q[3]_i_2__0_n_0 ),
        .O(wrap_unaligned_len[1]));
  LUT6 #(
    .INIT(64'hA8A8A8A8A8A8A808)) 
    \wrap_unaligned_len_q[2]_i_1__0 
       (.I0(s_axi_araddr[4]),
        .I1(\masked_addr_q[4]_i_2__0_n_0 ),
        .I2(s_axi_arsize[2]),
        .I3(s_axi_arsize[0]),
        .I4(s_axi_arlen[0]),
        .I5(s_axi_arsize[1]),
        .O(wrap_unaligned_len[2]));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wrap_unaligned_len_q[3]_i_1__0 
       (.I0(s_axi_araddr[5]),
        .I1(\masked_addr_q[5]_i_2__0_n_0 ),
        .O(wrap_unaligned_len[3]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT4 #(
    .INIT(16'hB800)) 
    \wrap_unaligned_len_q[4]_i_1__0 
       (.I0(\masked_addr_q[6]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\num_transactions_q[0]_i_2__0_n_0 ),
        .I3(s_axi_araddr[6]),
        .O(wrap_unaligned_len[4]));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT4 #(
    .INIT(16'hB800)) 
    \wrap_unaligned_len_q[5]_i_1__0 
       (.I0(\masked_addr_q[7]_i_2__0_n_0 ),
        .I1(s_axi_arsize[2]),
        .I2(\masked_addr_q[7]_i_3__0_n_0 ),
        .I3(s_axi_araddr[7]),
        .O(wrap_unaligned_len[5]));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wrap_unaligned_len_q[6]_i_1__0 
       (.I0(s_axi_araddr[8]),
        .I1(\masked_addr_q[8]_i_2__0_n_0 ),
        .O(wrap_unaligned_len[6]));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wrap_unaligned_len_q[7]_i_1__0 
       (.I0(s_axi_araddr[9]),
        .I1(\masked_addr_q[9]_i_2__0_n_0 ),
        .O(wrap_unaligned_len[7]));
  FDRE \wrap_unaligned_len_q_reg[0] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[0]),
        .Q(wrap_unaligned_len_q[0]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[1] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[1]),
        .Q(wrap_unaligned_len_q[1]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[2] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[2]),
        .Q(wrap_unaligned_len_q[2]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[3] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[3]),
        .Q(wrap_unaligned_len_q[3]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[4] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[4]),
        .Q(wrap_unaligned_len_q[4]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[5] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[5]),
        .Q(wrap_unaligned_len_q[5]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[6] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[6]),
        .Q(wrap_unaligned_len_q[6]),
        .R(SR));
  FDRE \wrap_unaligned_len_q_reg[7] 
       (.C(CLK),
        .CE(S_AXI_AREADY_I_reg_0),
        .D(wrap_unaligned_len[7]),
        .Q(wrap_unaligned_len_q[7]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_29_axi_downsizer" *) 
module design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_axi_downsizer
   (E,
    command_ongoing_reg,
    S_AXI_AREADY_I_reg,
    command_ongoing_reg_0,
    s_axi_rdata,
    s_axi_bresp,
    din,
    s_axi_bid,
    m_axi_awcache,
    m_axi_awprot,
    m_axi_awregion,
    m_axi_awqos,
    \goreg_dm.dout_i_reg[9] ,
    access_fit_mi_side_q_reg,
    s_axi_rid,
    m_axi_arcache,
    m_axi_arprot,
    m_axi_arregion,
    m_axi_arqos,
    s_axi_rresp,
    s_axi_bvalid,
    m_axi_bready,
    m_axi_awlock,
    m_axi_awaddr,
    m_axi_wvalid,
    s_axi_wready,
    m_axi_arlock,
    m_axi_araddr,
    s_axi_rvalid,
    m_axi_rready,
    m_axi_awburst,
    m_axi_wdata,
    m_axi_wstrb,
    m_axi_arburst,
    s_axi_rlast,
    s_axi_awsize,
    s_axi_awlen,
    s_axi_arsize,
    s_axi_arlen,
    s_axi_awburst,
    s_axi_arburst,
    s_axi_awvalid,
    m_axi_awready,
    out,
    s_axi_awaddr,
    s_axi_arvalid,
    m_axi_arready,
    s_axi_araddr,
    m_axi_rvalid,
    s_axi_rready,
    m_axi_rdata,
    CLK,
    s_axi_awid,
    s_axi_awlock,
    s_axi_awcache,
    s_axi_awprot,
    s_axi_awregion,
    s_axi_awqos,
    s_axi_arid,
    s_axi_arlock,
    s_axi_arcache,
    s_axi_arprot,
    s_axi_arregion,
    s_axi_arqos,
    m_axi_rlast,
    m_axi_bvalid,
    s_axi_bready,
    s_axi_wvalid,
    m_axi_wready,
    m_axi_rresp,
    m_axi_bresp,
    s_axi_wdata,
    s_axi_wstrb);
  output [0:0]E;
  output command_ongoing_reg;
  output [0:0]S_AXI_AREADY_I_reg;
  output command_ongoing_reg_0;
  output [127:0]s_axi_rdata;
  output [1:0]s_axi_bresp;
  output [10:0]din;
  output [15:0]s_axi_bid;
  output [3:0]m_axi_awcache;
  output [2:0]m_axi_awprot;
  output [3:0]m_axi_awregion;
  output [3:0]m_axi_awqos;
  output \goreg_dm.dout_i_reg[9] ;
  output [10:0]access_fit_mi_side_q_reg;
  output [15:0]s_axi_rid;
  output [3:0]m_axi_arcache;
  output [2:0]m_axi_arprot;
  output [3:0]m_axi_arregion;
  output [3:0]m_axi_arqos;
  output [1:0]s_axi_rresp;
  output s_axi_bvalid;
  output m_axi_bready;
  output [0:0]m_axi_awlock;
  output [39:0]m_axi_awaddr;
  output m_axi_wvalid;
  output s_axi_wready;
  output [0:0]m_axi_arlock;
  output [39:0]m_axi_araddr;
  output s_axi_rvalid;
  output m_axi_rready;
  output [1:0]m_axi_awburst;
  output [31:0]m_axi_wdata;
  output [3:0]m_axi_wstrb;
  output [1:0]m_axi_arburst;
  output s_axi_rlast;
  input [2:0]s_axi_awsize;
  input [7:0]s_axi_awlen;
  input [2:0]s_axi_arsize;
  input [7:0]s_axi_arlen;
  input [1:0]s_axi_awburst;
  input [1:0]s_axi_arburst;
  input s_axi_awvalid;
  input m_axi_awready;
  input out;
  input [39:0]s_axi_awaddr;
  input s_axi_arvalid;
  input m_axi_arready;
  input [39:0]s_axi_araddr;
  input m_axi_rvalid;
  input s_axi_rready;
  input [31:0]m_axi_rdata;
  input CLK;
  input [15:0]s_axi_awid;
  input [0:0]s_axi_awlock;
  input [3:0]s_axi_awcache;
  input [2:0]s_axi_awprot;
  input [3:0]s_axi_awregion;
  input [3:0]s_axi_awqos;
  input [15:0]s_axi_arid;
  input [0:0]s_axi_arlock;
  input [3:0]s_axi_arcache;
  input [2:0]s_axi_arprot;
  input [3:0]s_axi_arregion;
  input [3:0]s_axi_arqos;
  input m_axi_rlast;
  input m_axi_bvalid;
  input s_axi_bready;
  input s_axi_wvalid;
  input m_axi_wready;
  input [1:0]m_axi_rresp;
  input [1:0]m_axi_bresp;
  input [127:0]s_axi_wdata;
  input [15:0]s_axi_wstrb;

  wire CLK;
  wire [0:0]E;
  wire [0:0]S_AXI_AREADY_I_reg;
  wire S_AXI_RDATA_II;
  wire \USE_B_CHANNEL.cmd_b_queue/inst/empty ;
  wire [3:0]\USE_READ.rd_cmd_first_word ;
  wire \USE_READ.rd_cmd_fix ;
  wire [7:0]\USE_READ.rd_cmd_length ;
  wire \USE_READ.rd_cmd_mirror ;
  wire [2:0]\USE_READ.rd_cmd_offset ;
  wire \USE_READ.read_addr_inst_n_231 ;
  wire \USE_READ.read_addr_inst_n_32 ;
  wire \USE_READ.read_data_inst_n_1 ;
  wire \USE_READ.read_data_inst_n_11 ;
  wire \USE_READ.read_data_inst_n_12 ;
  wire \USE_READ.read_data_inst_n_13 ;
  wire \USE_READ.read_data_inst_n_4 ;
  wire \USE_READ.read_data_inst_n_5 ;
  wire \USE_READ.read_data_inst_n_6 ;
  wire \USE_READ.read_data_inst_n_7 ;
  wire \USE_READ.read_data_inst_n_8 ;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire [3:0]\USE_WRITE.wr_cmd_b_repeat ;
  wire \USE_WRITE.wr_cmd_b_split ;
  wire [3:0]\USE_WRITE.wr_cmd_first_word ;
  wire \USE_WRITE.wr_cmd_fix ;
  wire [7:0]\USE_WRITE.wr_cmd_length ;
  wire \USE_WRITE.write_addr_inst_n_140 ;
  wire \USE_WRITE.write_addr_inst_n_6 ;
  wire \USE_WRITE.write_data_inst_n_2 ;
  wire \USE_WRITE.write_data_inst_n_3 ;
  wire \USE_WRITE.write_data_inst_n_4 ;
  wire \USE_WRITE.write_data_inst_n_5 ;
  wire \USE_WRITE.write_data_inst_n_9 ;
  wire \WORD_LANE[0].S_AXI_RDATA_II_reg0 ;
  wire \WORD_LANE[1].S_AXI_RDATA_II_reg0 ;
  wire \WORD_LANE[2].S_AXI_RDATA_II_reg0 ;
  wire \WORD_LANE[3].S_AXI_RDATA_II_reg0 ;
  wire [10:0]access_fit_mi_side_q_reg;
  wire [1:0]areset_d;
  wire [2:0]cmd_size_ii;
  wire [2:0]cmd_size_ii_1;
  wire command_ongoing_reg;
  wire command_ongoing_reg_0;
  wire [3:0]current_word_1;
  wire [3:0]current_word_1_2;
  wire [10:0]din;
  wire first_mi_word;
  wire first_mi_word_3;
  wire \goreg_dm.dout_i_reg[9] ;
  wire [39:0]m_axi_araddr;
  wire [1:0]m_axi_arburst;
  wire [3:0]m_axi_arcache;
  wire [0:0]m_axi_arlock;
  wire [2:0]m_axi_arprot;
  wire [3:0]m_axi_arqos;
  wire m_axi_arready;
  wire [3:0]m_axi_arregion;
  wire [39:0]m_axi_awaddr;
  wire [1:0]m_axi_awburst;
  wire [3:0]m_axi_awcache;
  wire [0:0]m_axi_awlock;
  wire [2:0]m_axi_awprot;
  wire [3:0]m_axi_awqos;
  wire m_axi_awready;
  wire [3:0]m_axi_awregion;
  wire m_axi_bready;
  wire [1:0]m_axi_bresp;
  wire m_axi_bvalid;
  wire [31:0]m_axi_rdata;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire [1:0]m_axi_rresp;
  wire m_axi_rvalid;
  wire [31:0]m_axi_wdata;
  wire m_axi_wready;
  wire [3:0]m_axi_wstrb;
  wire m_axi_wvalid;
  wire out;
  wire [3:0]p_0_in;
  wire [3:0]p_0_in_0;
  wire p_2_in;
  wire [127:0]p_3_in;
  wire p_7_in;
  wire [39:0]s_axi_araddr;
  wire [1:0]s_axi_arburst;
  wire [3:0]s_axi_arcache;
  wire [15:0]s_axi_arid;
  wire [7:0]s_axi_arlen;
  wire [0:0]s_axi_arlock;
  wire [2:0]s_axi_arprot;
  wire [3:0]s_axi_arqos;
  wire [3:0]s_axi_arregion;
  wire [2:0]s_axi_arsize;
  wire s_axi_arvalid;
  wire [39:0]s_axi_awaddr;
  wire [1:0]s_axi_awburst;
  wire [3:0]s_axi_awcache;
  wire [15:0]s_axi_awid;
  wire [7:0]s_axi_awlen;
  wire [0:0]s_axi_awlock;
  wire [2:0]s_axi_awprot;
  wire [3:0]s_axi_awqos;
  wire [3:0]s_axi_awregion;
  wire [2:0]s_axi_awsize;
  wire s_axi_awvalid;
  wire [15:0]s_axi_bid;
  wire s_axi_bready;
  wire [1:0]s_axi_bresp;
  wire s_axi_bvalid;
  wire [127:0]s_axi_rdata;
  wire [15:0]s_axi_rid;
  wire s_axi_rlast;
  wire s_axi_rready;
  wire [1:0]s_axi_rresp;
  wire s_axi_rvalid;
  wire [127:0]s_axi_wdata;
  wire s_axi_wready;
  wire [15:0]s_axi_wstrb;
  wire s_axi_wvalid;

  design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_a_downsizer__parameterized0 \USE_READ.read_addr_inst 
       (.CLK(CLK),
        .D(p_0_in),
        .E(\WORD_LANE[3].S_AXI_RDATA_II_reg0 ),
        .Q({current_word_1[3],current_word_1[0]}),
        .SR(\USE_WRITE.write_addr_inst_n_6 ),
        .S_AXI_AREADY_I_reg_0(S_AXI_AREADY_I_reg),
        .S_AXI_AREADY_I_reg_1(\USE_WRITE.write_addr_inst_n_140 ),
        .\S_AXI_RRESP_ACC_reg[0] (\USE_READ.read_data_inst_n_8 ),
        .\S_AXI_RRESP_ACC_reg[0]_0 (\USE_READ.read_data_inst_n_13 ),
        .\WORD_LANE[3].S_AXI_RDATA_II_reg[127] (\USE_READ.read_data_inst_n_11 ),
        .access_fit_mi_side_q_reg_0(access_fit_mi_side_q_reg),
        .areset_d(areset_d),
        .command_ongoing_reg_0(command_ongoing_reg_0),
        .\current_word_1_reg[1] (\USE_READ.read_data_inst_n_6 ),
        .\current_word_1_reg[1]_0 (\USE_READ.read_data_inst_n_5 ),
        .\current_word_1_reg[2] (\USE_READ.read_data_inst_n_7 ),
        .\current_word_1_reg[3] (\USE_READ.read_data_inst_n_4 ),
        .dout({\USE_READ.rd_cmd_fix ,\USE_READ.rd_cmd_mirror ,\USE_READ.rd_cmd_first_word ,\USE_READ.rd_cmd_offset ,cmd_size_ii,\USE_READ.rd_cmd_length }),
        .first_mi_word(first_mi_word),
        .\goreg_dm.dout_i_reg[2] (\USE_READ.read_addr_inst_n_231 ),
        .m_axi_araddr(m_axi_araddr),
        .m_axi_arburst(m_axi_arburst),
        .m_axi_arcache(m_axi_arcache),
        .m_axi_arlock(m_axi_arlock),
        .m_axi_arprot(m_axi_arprot),
        .m_axi_arqos(m_axi_arqos),
        .m_axi_arready(m_axi_arready),
        .m_axi_arready_0(\USE_READ.read_addr_inst_n_32 ),
        .m_axi_arregion(m_axi_arregion),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_rvalid_0(\WORD_LANE[2].S_AXI_RDATA_II_reg0 ),
        .m_axi_rvalid_1(\WORD_LANE[1].S_AXI_RDATA_II_reg0 ),
        .m_axi_rvalid_2(\WORD_LANE[0].S_AXI_RDATA_II_reg0 ),
        .m_axi_rvalid_3(p_7_in),
        .out(out),
        .p_3_in(p_3_in),
        .s_axi_araddr(s_axi_araddr),
        .s_axi_arburst(s_axi_arburst),
        .s_axi_arcache(s_axi_arcache),
        .s_axi_aresetn(S_AXI_RDATA_II),
        .s_axi_arid(s_axi_arid),
        .s_axi_arlen(s_axi_arlen),
        .s_axi_arlock(s_axi_arlock),
        .s_axi_arprot(s_axi_arprot),
        .s_axi_arqos(s_axi_arqos),
        .s_axi_arregion(s_axi_arregion),
        .s_axi_arsize(s_axi_arsize),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_rdata(s_axi_rdata),
        .\s_axi_rdata[127]_INST_0_i_2 (\USE_READ.read_data_inst_n_12 ),
        .s_axi_rid(s_axi_rid),
        .s_axi_rlast(s_axi_rlast),
        .s_axi_rready(s_axi_rready),
        .s_axi_rvalid(s_axi_rvalid),
        .s_axi_rvalid_0(\USE_READ.read_data_inst_n_1 ));
  design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_r_downsizer \USE_READ.read_data_inst 
       (.CLK(CLK),
        .D(p_0_in),
        .E(p_7_in),
        .Q({current_word_1[3],current_word_1[0]}),
        .SR(\USE_WRITE.write_addr_inst_n_6 ),
        .\S_AXI_RRESP_ACC_reg[0]_0 (\USE_READ.read_addr_inst_n_231 ),
        .\S_AXI_RRESP_ACC_reg[1]_0 (\USE_READ.read_data_inst_n_13 ),
        .\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 (S_AXI_RDATA_II),
        .\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 (\WORD_LANE[0].S_AXI_RDATA_II_reg0 ),
        .\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 (\WORD_LANE[1].S_AXI_RDATA_II_reg0 ),
        .\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 (\WORD_LANE[2].S_AXI_RDATA_II_reg0 ),
        .\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 (\WORD_LANE[3].S_AXI_RDATA_II_reg0 ),
        .\current_word_1_reg[0]_0 (\USE_READ.read_data_inst_n_6 ),
        .\current_word_1_reg[1]_0 (\USE_READ.read_data_inst_n_5 ),
        .\current_word_1_reg[2]_0 (\USE_READ.read_data_inst_n_7 ),
        .\current_word_1_reg[3]_0 (\USE_READ.read_data_inst_n_8 ),
        .dout({\USE_READ.rd_cmd_fix ,\USE_READ.rd_cmd_mirror ,\USE_READ.rd_cmd_first_word ,\USE_READ.rd_cmd_offset ,cmd_size_ii,\USE_READ.rd_cmd_length }),
        .first_mi_word(first_mi_word),
        .first_word_reg_0(\USE_READ.read_data_inst_n_12 ),
        .\goreg_dm.dout_i_reg[12] (\USE_READ.read_data_inst_n_4 ),
        .\goreg_dm.dout_i_reg[19] (\USE_READ.read_data_inst_n_11 ),
        .\goreg_dm.dout_i_reg[9] (\USE_READ.read_data_inst_n_1 ),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rresp(m_axi_rresp),
        .p_3_in(p_3_in),
        .s_axi_rresp(s_axi_rresp));
  design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_b_downsizer \USE_WRITE.USE_SPLIT.write_resp_inst 
       (.CLK(CLK),
        .SR(\USE_WRITE.write_addr_inst_n_6 ),
        .\USE_WRITE.wr_cmd_b_ready (\USE_WRITE.wr_cmd_b_ready ),
        .dout({\USE_WRITE.wr_cmd_b_split ,\USE_WRITE.wr_cmd_b_repeat }),
        .empty(\USE_B_CHANNEL.cmd_b_queue/inst/empty ),
        .m_axi_bready(m_axi_bready),
        .m_axi_bresp(m_axi_bresp),
        .m_axi_bvalid(m_axi_bvalid),
        .s_axi_bready(s_axi_bready),
        .s_axi_bresp(s_axi_bresp),
        .s_axi_bvalid(s_axi_bvalid));
  design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_a_downsizer \USE_WRITE.write_addr_inst 
       (.CLK(CLK),
        .D(p_0_in_0),
        .E(p_2_in),
        .Q({current_word_1_2[3:2],current_word_1_2[0]}),
        .SR(\USE_WRITE.write_addr_inst_n_6 ),
        .S_AXI_AREADY_I_reg_0(E),
        .S_AXI_AREADY_I_reg_1(\USE_READ.read_addr_inst_n_32 ),
        .S_AXI_AREADY_I_reg_2(S_AXI_AREADY_I_reg),
        .\USE_WRITE.wr_cmd_b_ready (\USE_WRITE.wr_cmd_b_ready ),
        .areset_d(areset_d),
        .\areset_d_reg[0]_0 (\USE_WRITE.write_addr_inst_n_140 ),
        .command_ongoing_reg_0(command_ongoing_reg),
        .\current_word_1_reg[1] (\USE_WRITE.write_data_inst_n_3 ),
        .\current_word_1_reg[1]_0 (\USE_WRITE.write_data_inst_n_4 ),
        .\current_word_1_reg[2] (\USE_WRITE.write_data_inst_n_5 ),
        .\current_word_1_reg[3] (\USE_WRITE.write_data_inst_n_2 ),
        .din(din),
        .dout({\USE_WRITE.wr_cmd_b_split ,\USE_WRITE.wr_cmd_b_repeat }),
        .empty(\USE_B_CHANNEL.cmd_b_queue/inst/empty ),
        .first_mi_word(first_mi_word_3),
        .\goreg_dm.dout_i_reg[28] ({\USE_WRITE.wr_cmd_fix ,\USE_WRITE.wr_cmd_first_word ,cmd_size_ii_1,\USE_WRITE.wr_cmd_length }),
        .m_axi_awaddr(m_axi_awaddr),
        .m_axi_awburst(m_axi_awburst),
        .m_axi_awcache(m_axi_awcache),
        .m_axi_awlock(m_axi_awlock),
        .m_axi_awprot(m_axi_awprot),
        .m_axi_awqos(m_axi_awqos),
        .m_axi_awready(m_axi_awready),
        .m_axi_awregion(m_axi_awregion),
        .m_axi_wdata(m_axi_wdata),
        .m_axi_wready(m_axi_wready),
        .m_axi_wstrb(m_axi_wstrb),
        .m_axi_wstrb_3_sp_1(\USE_WRITE.write_data_inst_n_9 ),
        .m_axi_wvalid(m_axi_wvalid),
        .out(out),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_awaddr(s_axi_awaddr),
        .s_axi_awburst(s_axi_awburst),
        .s_axi_awcache(s_axi_awcache),
        .s_axi_awid(s_axi_awid),
        .s_axi_awlen(s_axi_awlen),
        .s_axi_awlock(s_axi_awlock),
        .s_axi_awprot(s_axi_awprot),
        .s_axi_awqos(s_axi_awqos),
        .s_axi_awregion(s_axi_awregion),
        .s_axi_awsize(s_axi_awsize),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_bid(s_axi_bid),
        .s_axi_wdata(s_axi_wdata),
        .s_axi_wready(s_axi_wready),
        .s_axi_wready_0(\goreg_dm.dout_i_reg[9] ),
        .s_axi_wstrb(s_axi_wstrb),
        .s_axi_wvalid(s_axi_wvalid));
  design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_w_downsizer \USE_WRITE.write_data_inst 
       (.CLK(CLK),
        .D(p_0_in_0),
        .E(p_2_in),
        .Q({current_word_1_2[3:2],current_word_1_2[0]}),
        .SR(\USE_WRITE.write_addr_inst_n_6 ),
        .\current_word_1_reg[0]_0 (\USE_WRITE.write_data_inst_n_4 ),
        .\current_word_1_reg[1]_0 (\USE_WRITE.write_data_inst_n_3 ),
        .\current_word_1_reg[1]_1 ({\USE_WRITE.wr_cmd_fix ,\USE_WRITE.wr_cmd_first_word ,cmd_size_ii_1,\USE_WRITE.wr_cmd_length }),
        .\current_word_1_reg[2]_0 (\USE_WRITE.write_data_inst_n_5 ),
        .\current_word_1_reg[3]_0 (\USE_WRITE.write_data_inst_n_9 ),
        .first_mi_word(first_mi_word_3),
        .\goreg_dm.dout_i_reg[12] (\USE_WRITE.write_data_inst_n_2 ),
        .\goreg_dm.dout_i_reg[9] (\goreg_dm.dout_i_reg[9] ));
endmodule

(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_29_b_downsizer" *) 
module design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_b_downsizer
   (\USE_WRITE.wr_cmd_b_ready ,
    s_axi_bvalid,
    m_axi_bready,
    s_axi_bresp,
    SR,
    CLK,
    dout,
    m_axi_bvalid,
    s_axi_bready,
    empty,
    m_axi_bresp);
  output \USE_WRITE.wr_cmd_b_ready ;
  output s_axi_bvalid;
  output m_axi_bready;
  output [1:0]s_axi_bresp;
  input [0:0]SR;
  input CLK;
  input [4:0]dout;
  input m_axi_bvalid;
  input s_axi_bready;
  input empty;
  input [1:0]m_axi_bresp;

  wire CLK;
  wire [0:0]SR;
  wire [1:0]S_AXI_BRESP_ACC;
  wire \USE_WRITE.wr_cmd_b_ready ;
  wire [4:0]dout;
  wire empty;
  wire first_mi_word;
  wire last_word;
  wire m_axi_bready;
  wire [1:0]m_axi_bresp;
  wire m_axi_bvalid;
  wire [7:0]next_repeat_cnt;
  wire p_1_in;
  wire \repeat_cnt[1]_i_1_n_0 ;
  wire \repeat_cnt[2]_i_2_n_0 ;
  wire \repeat_cnt[3]_i_2_n_0 ;
  wire \repeat_cnt[5]_i_2_n_0 ;
  wire \repeat_cnt[7]_i_2_n_0 ;
  wire [7:0]repeat_cnt_reg;
  wire s_axi_bready;
  wire [1:0]s_axi_bresp;
  wire s_axi_bvalid;
  wire s_axi_bvalid_INST_0_i_1_n_0;
  wire s_axi_bvalid_INST_0_i_2_n_0;

  FDRE \S_AXI_BRESP_ACC_reg[0] 
       (.C(CLK),
        .CE(p_1_in),
        .D(s_axi_bresp[0]),
        .Q(S_AXI_BRESP_ACC[0]),
        .R(SR));
  FDRE \S_AXI_BRESP_ACC_reg[1] 
       (.C(CLK),
        .CE(p_1_in),
        .D(s_axi_bresp[1]),
        .Q(S_AXI_BRESP_ACC[1]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    fifo_gen_inst_i_7
       (.I0(s_axi_bvalid_INST_0_i_1_n_0),
        .I1(m_axi_bvalid),
        .I2(s_axi_bready),
        .I3(empty),
        .O(\USE_WRITE.wr_cmd_b_ready ));
  LUT3 #(
    .INIT(8'hA8)) 
    first_mi_word_i_1
       (.I0(m_axi_bvalid),
        .I1(s_axi_bvalid_INST_0_i_1_n_0),
        .I2(s_axi_bready),
        .O(p_1_in));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT1 #(
    .INIT(2'h1)) 
    first_mi_word_i_2
       (.I0(s_axi_bvalid_INST_0_i_1_n_0),
        .O(last_word));
  FDSE first_mi_word_reg
       (.C(CLK),
        .CE(p_1_in),
        .D(last_word),
        .Q(first_mi_word),
        .S(SR));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT2 #(
    .INIT(4'hE)) 
    m_axi_bready_INST_0
       (.I0(s_axi_bvalid_INST_0_i_1_n_0),
        .I1(s_axi_bready),
        .O(m_axi_bready));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'h1D)) 
    \repeat_cnt[0]_i_1 
       (.I0(repeat_cnt_reg[0]),
        .I1(first_mi_word),
        .I2(dout[0]),
        .O(next_repeat_cnt[0]));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT5 #(
    .INIT(32'hCCA533A5)) 
    \repeat_cnt[1]_i_1 
       (.I0(repeat_cnt_reg[1]),
        .I1(dout[1]),
        .I2(repeat_cnt_reg[0]),
        .I3(first_mi_word),
        .I4(dout[0]),
        .O(\repeat_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEFA051111FA05)) 
    \repeat_cnt[2]_i_1 
       (.I0(\repeat_cnt[2]_i_2_n_0 ),
        .I1(dout[1]),
        .I2(repeat_cnt_reg[1]),
        .I3(repeat_cnt_reg[2]),
        .I4(first_mi_word),
        .I5(dout[2]),
        .O(next_repeat_cnt[2]));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \repeat_cnt[2]_i_2 
       (.I0(dout[0]),
        .I1(first_mi_word),
        .I2(repeat_cnt_reg[0]),
        .O(\repeat_cnt[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFAFCF305050CF30)) 
    \repeat_cnt[3]_i_1 
       (.I0(dout[2]),
        .I1(repeat_cnt_reg[2]),
        .I2(\repeat_cnt[3]_i_2_n_0 ),
        .I3(repeat_cnt_reg[3]),
        .I4(first_mi_word),
        .I5(dout[3]),
        .O(next_repeat_cnt[3]));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT5 #(
    .INIT(32'h00053305)) 
    \repeat_cnt[3]_i_2 
       (.I0(repeat_cnt_reg[1]),
        .I1(dout[1]),
        .I2(repeat_cnt_reg[0]),
        .I3(first_mi_word),
        .I4(dout[0]),
        .O(\repeat_cnt[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h3A350A0A)) 
    \repeat_cnt[4]_i_1 
       (.I0(repeat_cnt_reg[4]),
        .I1(dout[3]),
        .I2(first_mi_word),
        .I3(repeat_cnt_reg[3]),
        .I4(\repeat_cnt[5]_i_2_n_0 ),
        .O(next_repeat_cnt[4]));
  LUT6 #(
    .INIT(64'h0A0A090AFA0AF90A)) 
    \repeat_cnt[5]_i_1 
       (.I0(repeat_cnt_reg[5]),
        .I1(repeat_cnt_reg[4]),
        .I2(first_mi_word),
        .I3(\repeat_cnt[5]_i_2_n_0 ),
        .I4(repeat_cnt_reg[3]),
        .I5(dout[3]),
        .O(next_repeat_cnt[5]));
  LUT6 #(
    .INIT(64'h0000000511110005)) 
    \repeat_cnt[5]_i_2 
       (.I0(\repeat_cnt[2]_i_2_n_0 ),
        .I1(dout[1]),
        .I2(repeat_cnt_reg[1]),
        .I3(repeat_cnt_reg[2]),
        .I4(first_mi_word),
        .I5(dout[2]),
        .O(\repeat_cnt[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFA0AF90A)) 
    \repeat_cnt[6]_i_1 
       (.I0(repeat_cnt_reg[6]),
        .I1(repeat_cnt_reg[5]),
        .I2(first_mi_word),
        .I3(\repeat_cnt[7]_i_2_n_0 ),
        .I4(repeat_cnt_reg[4]),
        .O(next_repeat_cnt[6]));
  LUT6 #(
    .INIT(64'hFAFA0A0AFAF90A0A)) 
    \repeat_cnt[7]_i_1 
       (.I0(repeat_cnt_reg[7]),
        .I1(repeat_cnt_reg[6]),
        .I2(first_mi_word),
        .I3(repeat_cnt_reg[4]),
        .I4(\repeat_cnt[7]_i_2_n_0 ),
        .I5(repeat_cnt_reg[5]),
        .O(next_repeat_cnt[7]));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    \repeat_cnt[7]_i_2 
       (.I0(dout[2]),
        .I1(repeat_cnt_reg[2]),
        .I2(\repeat_cnt[3]_i_2_n_0 ),
        .I3(repeat_cnt_reg[3]),
        .I4(first_mi_word),
        .I5(dout[3]),
        .O(\repeat_cnt[7]_i_2_n_0 ));
  FDRE \repeat_cnt_reg[0] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[0]),
        .Q(repeat_cnt_reg[0]),
        .R(SR));
  FDRE \repeat_cnt_reg[1] 
       (.C(CLK),
        .CE(p_1_in),
        .D(\repeat_cnt[1]_i_1_n_0 ),
        .Q(repeat_cnt_reg[1]),
        .R(SR));
  FDRE \repeat_cnt_reg[2] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[2]),
        .Q(repeat_cnt_reg[2]),
        .R(SR));
  FDRE \repeat_cnt_reg[3] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[3]),
        .Q(repeat_cnt_reg[3]),
        .R(SR));
  FDRE \repeat_cnt_reg[4] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[4]),
        .Q(repeat_cnt_reg[4]),
        .R(SR));
  FDRE \repeat_cnt_reg[5] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[5]),
        .Q(repeat_cnt_reg[5]),
        .R(SR));
  FDRE \repeat_cnt_reg[6] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[6]),
        .Q(repeat_cnt_reg[6]),
        .R(SR));
  FDRE \repeat_cnt_reg[7] 
       (.C(CLK),
        .CE(p_1_in),
        .D(next_repeat_cnt[7]),
        .Q(repeat_cnt_reg[7]),
        .R(SR));
  LUT6 #(
    .INIT(64'hAAAAAAAAECAEAAAA)) 
    \s_axi_bresp[0]_INST_0 
       (.I0(m_axi_bresp[0]),
        .I1(S_AXI_BRESP_ACC[0]),
        .I2(m_axi_bresp[1]),
        .I3(S_AXI_BRESP_ACC[1]),
        .I4(dout[4]),
        .I5(first_mi_word),
        .O(s_axi_bresp[0]));
  LUT4 #(
    .INIT(16'hAEAA)) 
    \s_axi_bresp[1]_INST_0 
       (.I0(m_axi_bresp[1]),
        .I1(dout[4]),
        .I2(first_mi_word),
        .I3(S_AXI_BRESP_ACC[1]),
        .O(s_axi_bresp[1]));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT2 #(
    .INIT(4'h2)) 
    s_axi_bvalid_INST_0
       (.I0(m_axi_bvalid),
        .I1(s_axi_bvalid_INST_0_i_1_n_0),
        .O(s_axi_bvalid));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    s_axi_bvalid_INST_0_i_1
       (.I0(dout[4]),
        .I1(s_axi_bvalid_INST_0_i_2_n_0),
        .I2(repeat_cnt_reg[6]),
        .I3(repeat_cnt_reg[7]),
        .I4(repeat_cnt_reg[5]),
        .O(s_axi_bvalid_INST_0_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    s_axi_bvalid_INST_0_i_2
       (.I0(repeat_cnt_reg[3]),
        .I1(first_mi_word),
        .I2(repeat_cnt_reg[0]),
        .I3(repeat_cnt_reg[4]),
        .I4(repeat_cnt_reg[1]),
        .I5(repeat_cnt_reg[2]),
        .O(s_axi_bvalid_INST_0_i_2_n_0));
endmodule

(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_29_r_downsizer" *) 
module design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_r_downsizer
   (first_mi_word,
    \goreg_dm.dout_i_reg[9] ,
    s_axi_rresp,
    \goreg_dm.dout_i_reg[12] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1_reg[0]_0 ,
    \current_word_1_reg[2]_0 ,
    \current_word_1_reg[3]_0 ,
    Q,
    \goreg_dm.dout_i_reg[19] ,
    first_word_reg_0,
    \S_AXI_RRESP_ACC_reg[1]_0 ,
    p_3_in,
    SR,
    E,
    m_axi_rlast,
    CLK,
    dout,
    \S_AXI_RRESP_ACC_reg[0]_0 ,
    m_axi_rresp,
    D,
    \WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ,
    \WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ,
    m_axi_rdata,
    \WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ,
    \WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ,
    \WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 );
  output first_mi_word;
  output \goreg_dm.dout_i_reg[9] ;
  output [1:0]s_axi_rresp;
  output \goreg_dm.dout_i_reg[12] ;
  output \current_word_1_reg[1]_0 ;
  output \current_word_1_reg[0]_0 ;
  output \current_word_1_reg[2]_0 ;
  output \current_word_1_reg[3]_0 ;
  output [1:0]Q;
  output \goreg_dm.dout_i_reg[19] ;
  output first_word_reg_0;
  output \S_AXI_RRESP_ACC_reg[1]_0 ;
  output [127:0]p_3_in;
  input [0:0]SR;
  input [0:0]E;
  input m_axi_rlast;
  input CLK;
  input [19:0]dout;
  input \S_AXI_RRESP_ACC_reg[0]_0 ;
  input [1:0]m_axi_rresp;
  input [3:0]D;
  input [0:0]\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ;
  input [0:0]\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ;
  input [31:0]m_axi_rdata;
  input [0:0]\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ;
  input [0:0]\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ;
  input [0:0]\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ;

  wire CLK;
  wire [3:0]D;
  wire [0:0]E;
  wire [1:0]Q;
  wire [0:0]SR;
  wire [1:0]S_AXI_RRESP_ACC;
  wire \S_AXI_RRESP_ACC_reg[0]_0 ;
  wire \S_AXI_RRESP_ACC_reg[1]_0 ;
  wire [0:0]\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ;
  wire [0:0]\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ;
  wire [0:0]\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ;
  wire [0:0]\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ;
  wire [0:0]\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ;
  wire [2:1]current_word_1;
  wire \current_word_1_reg[0]_0 ;
  wire \current_word_1_reg[1]_0 ;
  wire \current_word_1_reg[2]_0 ;
  wire \current_word_1_reg[3]_0 ;
  wire [19:0]dout;
  wire first_mi_word;
  wire first_word_reg_0;
  wire \goreg_dm.dout_i_reg[12] ;
  wire \goreg_dm.dout_i_reg[19] ;
  wire \goreg_dm.dout_i_reg[9] ;
  wire \length_counter_1[1]_i_1__0_n_0 ;
  wire \length_counter_1[2]_i_2__0_n_0 ;
  wire \length_counter_1[3]_i_2__0_n_0 ;
  wire \length_counter_1[4]_i_2__0_n_0 ;
  wire \length_counter_1[5]_i_2_n_0 ;
  wire \length_counter_1[6]_i_2__0_n_0 ;
  wire [7:0]length_counter_1_reg;
  wire [31:0]m_axi_rdata;
  wire m_axi_rlast;
  wire [1:0]m_axi_rresp;
  wire [7:0]next_length_counter__0;
  wire [127:0]p_3_in;
  wire [1:0]s_axi_rresp;
  wire s_axi_rvalid_INST_0_i_3_n_0;

  FDRE \S_AXI_RRESP_ACC_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(s_axi_rresp[0]),
        .Q(S_AXI_RRESP_ACC[0]),
        .R(SR));
  FDRE \S_AXI_RRESP_ACC_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(s_axi_rresp[1]),
        .Q(S_AXI_RRESP_ACC[1]),
        .R(SR));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[0] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[0]),
        .Q(p_3_in[0]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[10] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[10]),
        .Q(p_3_in[10]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[11] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[11]),
        .Q(p_3_in[11]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[12] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[12]),
        .Q(p_3_in[12]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[13] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[13]),
        .Q(p_3_in[13]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[14] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[14]),
        .Q(p_3_in[14]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[15] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[15]),
        .Q(p_3_in[15]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[16] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[16]),
        .Q(p_3_in[16]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[17] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[17]),
        .Q(p_3_in[17]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[18] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[18]),
        .Q(p_3_in[18]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[19] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[19]),
        .Q(p_3_in[19]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[1] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[1]),
        .Q(p_3_in[1]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[20] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[20]),
        .Q(p_3_in[20]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[21] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[21]),
        .Q(p_3_in[21]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[22] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[22]),
        .Q(p_3_in[22]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[23] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[23]),
        .Q(p_3_in[23]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[24] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[24]),
        .Q(p_3_in[24]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[25] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[25]),
        .Q(p_3_in[25]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[26] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[26]),
        .Q(p_3_in[26]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[27] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[27]),
        .Q(p_3_in[27]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[28] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[28]),
        .Q(p_3_in[28]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[29] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[29]),
        .Q(p_3_in[29]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[2] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[2]),
        .Q(p_3_in[2]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[30] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[30]),
        .Q(p_3_in[30]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[31] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[31]),
        .Q(p_3_in[31]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[3] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[3]),
        .Q(p_3_in[3]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[4] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[4]),
        .Q(p_3_in[4]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[5] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[5]),
        .Q(p_3_in[5]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[6] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[6]),
        .Q(p_3_in[6]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[7] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[7]),
        .Q(p_3_in[7]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[8] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[8]),
        .Q(p_3_in[8]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[0].S_AXI_RDATA_II_reg[9] 
       (.C(CLK),
        .CE(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_1 ),
        .D(m_axi_rdata[9]),
        .Q(p_3_in[9]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[32] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[0]),
        .Q(p_3_in[32]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[33] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[1]),
        .Q(p_3_in[33]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[34] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[2]),
        .Q(p_3_in[34]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[35] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[3]),
        .Q(p_3_in[35]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[36] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[4]),
        .Q(p_3_in[36]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[37] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[5]),
        .Q(p_3_in[37]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[38] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[6]),
        .Q(p_3_in[38]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[39] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[7]),
        .Q(p_3_in[39]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[40] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[8]),
        .Q(p_3_in[40]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[41] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[9]),
        .Q(p_3_in[41]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[42] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[10]),
        .Q(p_3_in[42]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[43] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[11]),
        .Q(p_3_in[43]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[44] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[12]),
        .Q(p_3_in[44]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[45] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[13]),
        .Q(p_3_in[45]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[46] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[14]),
        .Q(p_3_in[46]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[47] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[15]),
        .Q(p_3_in[47]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[48] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[16]),
        .Q(p_3_in[48]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[49] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[17]),
        .Q(p_3_in[49]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[50] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[18]),
        .Q(p_3_in[50]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[51] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[19]),
        .Q(p_3_in[51]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[52] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[20]),
        .Q(p_3_in[52]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[53] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[21]),
        .Q(p_3_in[53]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[54] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[22]),
        .Q(p_3_in[54]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[55] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[23]),
        .Q(p_3_in[55]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[56] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[24]),
        .Q(p_3_in[56]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[57] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[25]),
        .Q(p_3_in[57]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[58] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[26]),
        .Q(p_3_in[58]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[59] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[27]),
        .Q(p_3_in[59]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[60] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[28]),
        .Q(p_3_in[60]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[61] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[29]),
        .Q(p_3_in[61]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[62] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[30]),
        .Q(p_3_in[62]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[1].S_AXI_RDATA_II_reg[63] 
       (.C(CLK),
        .CE(\WORD_LANE[1].S_AXI_RDATA_II_reg[63]_0 ),
        .D(m_axi_rdata[31]),
        .Q(p_3_in[63]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[64] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[0]),
        .Q(p_3_in[64]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[65] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[1]),
        .Q(p_3_in[65]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[66] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[2]),
        .Q(p_3_in[66]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[67] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[3]),
        .Q(p_3_in[67]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[68] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[4]),
        .Q(p_3_in[68]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[69] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[5]),
        .Q(p_3_in[69]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[70] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[6]),
        .Q(p_3_in[70]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[71] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[7]),
        .Q(p_3_in[71]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[72] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[8]),
        .Q(p_3_in[72]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[73] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[9]),
        .Q(p_3_in[73]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[74] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[10]),
        .Q(p_3_in[74]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[75] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[11]),
        .Q(p_3_in[75]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[76] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[12]),
        .Q(p_3_in[76]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[77] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[13]),
        .Q(p_3_in[77]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[78] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[14]),
        .Q(p_3_in[78]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[79] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[15]),
        .Q(p_3_in[79]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[80] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[16]),
        .Q(p_3_in[80]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[81] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[17]),
        .Q(p_3_in[81]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[82] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[18]),
        .Q(p_3_in[82]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[83] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[19]),
        .Q(p_3_in[83]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[84] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[20]),
        .Q(p_3_in[84]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[85] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[21]),
        .Q(p_3_in[85]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[86] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[22]),
        .Q(p_3_in[86]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[87] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[23]),
        .Q(p_3_in[87]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[88] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[24]),
        .Q(p_3_in[88]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[89] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[25]),
        .Q(p_3_in[89]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[90] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[26]),
        .Q(p_3_in[90]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[91] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[27]),
        .Q(p_3_in[91]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[92] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[28]),
        .Q(p_3_in[92]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[93] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[29]),
        .Q(p_3_in[93]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[94] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[30]),
        .Q(p_3_in[94]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[2].S_AXI_RDATA_II_reg[95] 
       (.C(CLK),
        .CE(\WORD_LANE[2].S_AXI_RDATA_II_reg[95]_0 ),
        .D(m_axi_rdata[31]),
        .Q(p_3_in[95]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[100] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[4]),
        .Q(p_3_in[100]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[101] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[5]),
        .Q(p_3_in[101]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[102] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[6]),
        .Q(p_3_in[102]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[103] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[7]),
        .Q(p_3_in[103]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[104] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[8]),
        .Q(p_3_in[104]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[105] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[9]),
        .Q(p_3_in[105]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[106] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[10]),
        .Q(p_3_in[106]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[107] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[11]),
        .Q(p_3_in[107]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[108] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[12]),
        .Q(p_3_in[108]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[109] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[13]),
        .Q(p_3_in[109]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[110] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[14]),
        .Q(p_3_in[110]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[111] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[15]),
        .Q(p_3_in[111]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[112] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[16]),
        .Q(p_3_in[112]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[113] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[17]),
        .Q(p_3_in[113]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[114] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[18]),
        .Q(p_3_in[114]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[115] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[19]),
        .Q(p_3_in[115]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[116] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[20]),
        .Q(p_3_in[116]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[117] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[21]),
        .Q(p_3_in[117]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[118] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[22]),
        .Q(p_3_in[118]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[119] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[23]),
        .Q(p_3_in[119]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[120] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[24]),
        .Q(p_3_in[120]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[121] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[25]),
        .Q(p_3_in[121]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[122] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[26]),
        .Q(p_3_in[122]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[123] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[27]),
        .Q(p_3_in[123]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[124] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[28]),
        .Q(p_3_in[124]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[125] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[29]),
        .Q(p_3_in[125]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[126] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[30]),
        .Q(p_3_in[126]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[127] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[31]),
        .Q(p_3_in[127]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[96] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[0]),
        .Q(p_3_in[96]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[97] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[1]),
        .Q(p_3_in[97]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[98] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[2]),
        .Q(p_3_in[98]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  FDRE \WORD_LANE[3].S_AXI_RDATA_II_reg[99] 
       (.C(CLK),
        .CE(\WORD_LANE[3].S_AXI_RDATA_II_reg[127]_0 ),
        .D(m_axi_rdata[3]),
        .Q(p_3_in[99]),
        .R(\WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0 ));
  LUT6 #(
    .INIT(64'h000A00F800000000)) 
    \current_word_1[3]_i_2 
       (.I0(\current_word_1_reg[1]_0 ),
        .I1(\current_word_1_reg[0]_0 ),
        .I2(dout[9]),
        .I3(dout[10]),
        .I4(dout[8]),
        .I5(\current_word_1_reg[2]_0 ),
        .O(\goreg_dm.dout_i_reg[12] ));
  FDRE \current_word_1_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(D[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE \current_word_1_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(D[1]),
        .Q(current_word_1[1]),
        .R(SR));
  FDRE \current_word_1_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(D[2]),
        .Q(current_word_1[2]),
        .R(SR));
  FDRE \current_word_1_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(D[3]),
        .Q(Q[1]),
        .R(SR));
  FDSE first_word_reg
       (.C(CLK),
        .CE(E),
        .D(m_axi_rlast),
        .Q(first_mi_word),
        .S(SR));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'h1D)) 
    \length_counter_1[0]_i_1__0 
       (.I0(length_counter_1_reg[0]),
        .I1(first_mi_word),
        .I2(dout[0]),
        .O(next_length_counter__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT5 #(
    .INIT(32'hCCA533A5)) 
    \length_counter_1[1]_i_1__0 
       (.I0(length_counter_1_reg[1]),
        .I1(dout[1]),
        .I2(length_counter_1_reg[0]),
        .I3(first_mi_word),
        .I4(dout[0]),
        .O(\length_counter_1[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEFA051111FA05)) 
    \length_counter_1[2]_i_1__0 
       (.I0(\length_counter_1[2]_i_2__0_n_0 ),
        .I1(dout[1]),
        .I2(length_counter_1_reg[1]),
        .I3(length_counter_1_reg[2]),
        .I4(first_mi_word),
        .I5(dout[2]),
        .O(next_length_counter__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \length_counter_1[2]_i_2__0 
       (.I0(dout[0]),
        .I1(first_mi_word),
        .I2(length_counter_1_reg[0]),
        .O(\length_counter_1[2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \length_counter_1[3]_i_1__0 
       (.I0(length_counter_1_reg[3]),
        .I1(dout[3]),
        .I2(dout[2]),
        .I3(first_mi_word),
        .I4(length_counter_1_reg[2]),
        .I5(\length_counter_1[3]_i_2__0_n_0 ),
        .O(next_length_counter__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT5 #(
    .INIT(32'h00053305)) 
    \length_counter_1[3]_i_2__0 
       (.I0(length_counter_1_reg[1]),
        .I1(dout[1]),
        .I2(length_counter_1_reg[0]),
        .I3(first_mi_word),
        .I4(dout[0]),
        .O(\length_counter_1[3]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hAFAFCF305050CF30)) 
    \length_counter_1[4]_i_1__0 
       (.I0(dout[3]),
        .I1(length_counter_1_reg[3]),
        .I2(\length_counter_1[4]_i_2__0_n_0 ),
        .I3(length_counter_1_reg[4]),
        .I4(first_mi_word),
        .I5(dout[4]),
        .O(next_length_counter__0[4]));
  LUT6 #(
    .INIT(64'h0000000511110005)) 
    \length_counter_1[4]_i_2__0 
       (.I0(\length_counter_1[2]_i_2__0_n_0 ),
        .I1(dout[1]),
        .I2(length_counter_1_reg[1]),
        .I3(length_counter_1_reg[2]),
        .I4(first_mi_word),
        .I5(dout[2]),
        .O(\length_counter_1[4]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \length_counter_1[5]_i_1__0 
       (.I0(length_counter_1_reg[5]),
        .I1(dout[5]),
        .I2(dout[4]),
        .I3(first_mi_word),
        .I4(length_counter_1_reg[4]),
        .I5(\length_counter_1[5]_i_2_n_0 ),
        .O(next_length_counter__0[5]));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    \length_counter_1[5]_i_2 
       (.I0(dout[2]),
        .I1(length_counter_1_reg[2]),
        .I2(\length_counter_1[3]_i_2__0_n_0 ),
        .I3(length_counter_1_reg[3]),
        .I4(first_mi_word),
        .I5(dout[3]),
        .O(\length_counter_1[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \length_counter_1[6]_i_1__0 
       (.I0(length_counter_1_reg[6]),
        .I1(dout[6]),
        .I2(dout[5]),
        .I3(first_mi_word),
        .I4(length_counter_1_reg[5]),
        .I5(\length_counter_1[6]_i_2__0_n_0 ),
        .O(next_length_counter__0[6]));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    \length_counter_1[6]_i_2__0 
       (.I0(dout[3]),
        .I1(length_counter_1_reg[3]),
        .I2(\length_counter_1[4]_i_2__0_n_0 ),
        .I3(length_counter_1_reg[4]),
        .I4(first_mi_word),
        .I5(dout[4]),
        .O(\length_counter_1[6]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \length_counter_1[7]_i_1__0 
       (.I0(length_counter_1_reg[7]),
        .I1(dout[7]),
        .I2(dout[6]),
        .I3(first_mi_word),
        .I4(length_counter_1_reg[6]),
        .I5(s_axi_rvalid_INST_0_i_3_n_0),
        .O(next_length_counter__0[7]));
  FDRE \length_counter_1_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[0]),
        .Q(length_counter_1_reg[0]),
        .R(SR));
  FDRE \length_counter_1_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\length_counter_1[1]_i_1__0_n_0 ),
        .Q(length_counter_1_reg[1]),
        .R(SR));
  FDRE \length_counter_1_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[2]),
        .Q(length_counter_1_reg[2]),
        .R(SR));
  FDRE \length_counter_1_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[3]),
        .Q(length_counter_1_reg[3]),
        .R(SR));
  FDRE \length_counter_1_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[4]),
        .Q(length_counter_1_reg[4]),
        .R(SR));
  FDRE \length_counter_1_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[5]),
        .Q(length_counter_1_reg[5]),
        .R(SR));
  FDRE \length_counter_1_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[6]),
        .Q(length_counter_1_reg[6]),
        .R(SR));
  FDRE \length_counter_1_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter__0[7]),
        .Q(length_counter_1_reg[7]),
        .R(SR));
  LUT6 #(
    .INIT(64'h1777E888E8881777)) 
    \s_axi_rdata[127]_INST_0_i_1 
       (.I0(\current_word_1_reg[1]_0 ),
        .I1(dout[12]),
        .I2(\current_word_1_reg[0]_0 ),
        .I3(dout[11]),
        .I4(\current_word_1_reg[2]_0 ),
        .I5(dout[13]),
        .O(\goreg_dm.dout_i_reg[19] ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT4 #(
    .INIT(16'hFE02)) 
    \s_axi_rdata[127]_INST_0_i_3 
       (.I0(current_word_1[1]),
        .I1(first_mi_word),
        .I2(dout[19]),
        .I3(dout[15]),
        .O(\current_word_1_reg[1]_0 ));
  LUT4 #(
    .INIT(16'hFE02)) 
    \s_axi_rdata[127]_INST_0_i_4 
       (.I0(Q[0]),
        .I1(first_mi_word),
        .I2(dout[19]),
        .I3(dout[14]),
        .O(\current_word_1_reg[0]_0 ));
  LUT4 #(
    .INIT(16'hFE02)) 
    \s_axi_rdata[127]_INST_0_i_5 
       (.I0(current_word_1[2]),
        .I1(first_mi_word),
        .I2(dout[19]),
        .I3(dout[16]),
        .O(\current_word_1_reg[2]_0 ));
  LUT4 #(
    .INIT(16'h01FD)) 
    \s_axi_rdata[127]_INST_0_i_7 
       (.I0(Q[1]),
        .I1(first_mi_word),
        .I2(dout[19]),
        .I3(dout[17]),
        .O(\current_word_1_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \s_axi_rdata[127]_INST_0_i_8 
       (.I0(first_mi_word),
        .I1(dout[19]),
        .O(first_word_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \s_axi_rresp[0]_INST_0 
       (.I0(S_AXI_RRESP_ACC[0]),
        .I1(\S_AXI_RRESP_ACC_reg[0]_0 ),
        .I2(m_axi_rresp[0]),
        .O(s_axi_rresp[0]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \s_axi_rresp[1]_INST_0 
       (.I0(S_AXI_RRESP_ACC[1]),
        .I1(\S_AXI_RRESP_ACC_reg[0]_0 ),
        .I2(m_axi_rresp[1]),
        .O(s_axi_rresp[1]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF7504)) 
    \s_axi_rresp[1]_INST_0_i_4 
       (.I0(S_AXI_RRESP_ACC[1]),
        .I1(S_AXI_RRESP_ACC[0]),
        .I2(m_axi_rresp[0]),
        .I3(m_axi_rresp[1]),
        .I4(dout[18]),
        .I5(first_mi_word),
        .O(\S_AXI_RRESP_ACC_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    s_axi_rvalid_INST_0_i_1
       (.I0(dout[6]),
        .I1(length_counter_1_reg[6]),
        .I2(s_axi_rvalid_INST_0_i_3_n_0),
        .I3(length_counter_1_reg[7]),
        .I4(first_mi_word),
        .I5(dout[7]),
        .O(\goreg_dm.dout_i_reg[9] ));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    s_axi_rvalid_INST_0_i_3
       (.I0(dout[4]),
        .I1(length_counter_1_reg[4]),
        .I2(\length_counter_1[5]_i_2_n_0 ),
        .I3(length_counter_1_reg[5]),
        .I4(first_mi_word),
        .I5(dout[5]),
        .O(s_axi_rvalid_INST_0_i_3_n_0));
endmodule

(* C_AXI_ADDR_WIDTH = "40" *) (* C_AXI_IS_ACLK_ASYNC = "0" *) (* C_AXI_PROTOCOL = "0" *) 
(* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_WRITE = "1" *) (* C_FAMILY = "zynquplus" *) 
(* C_FIFO_MODE = "0" *) (* C_MAX_SPLIT_BEATS = "256" *) (* C_M_AXI_ACLK_RATIO = "2" *) 
(* C_M_AXI_BYTES_LOG = "2" *) (* C_M_AXI_DATA_WIDTH = "32" *) (* C_PACKING_LEVEL = "1" *) 
(* C_RATIO = "4" *) (* C_RATIO_LOG = "2" *) (* C_SUPPORTS_ID = "1" *) 
(* C_SYNCHRONIZER_STAGE = "3" *) (* C_S_AXI_ACLK_RATIO = "1" *) (* C_S_AXI_BYTES_LOG = "4" *) 
(* C_S_AXI_DATA_WIDTH = "128" *) (* C_S_AXI_ID_WIDTH = "16" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_29_top" *) (* P_AXI3 = "1" *) (* P_AXI4 = "0" *) 
(* P_AXILITE = "2" *) (* P_CONVERSION = "2" *) (* P_MAX_SPLIT_BEATS = "256" *) 
module design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_top
   (s_axi_aclk,
    s_axi_aresetn,
    s_axi_awid,
    s_axi_awaddr,
    s_axi_awlen,
    s_axi_awsize,
    s_axi_awburst,
    s_axi_awlock,
    s_axi_awcache,
    s_axi_awprot,
    s_axi_awregion,
    s_axi_awqos,
    s_axi_awvalid,
    s_axi_awready,
    s_axi_wdata,
    s_axi_wstrb,
    s_axi_wlast,
    s_axi_wvalid,
    s_axi_wready,
    s_axi_bid,
    s_axi_bresp,
    s_axi_bvalid,
    s_axi_bready,
    s_axi_arid,
    s_axi_araddr,
    s_axi_arlen,
    s_axi_arsize,
    s_axi_arburst,
    s_axi_arlock,
    s_axi_arcache,
    s_axi_arprot,
    s_axi_arregion,
    s_axi_arqos,
    s_axi_arvalid,
    s_axi_arready,
    s_axi_rid,
    s_axi_rdata,
    s_axi_rresp,
    s_axi_rlast,
    s_axi_rvalid,
    s_axi_rready,
    m_axi_aclk,
    m_axi_aresetn,
    m_axi_awaddr,
    m_axi_awlen,
    m_axi_awsize,
    m_axi_awburst,
    m_axi_awlock,
    m_axi_awcache,
    m_axi_awprot,
    m_axi_awregion,
    m_axi_awqos,
    m_axi_awvalid,
    m_axi_awready,
    m_axi_wdata,
    m_axi_wstrb,
    m_axi_wlast,
    m_axi_wvalid,
    m_axi_wready,
    m_axi_bresp,
    m_axi_bvalid,
    m_axi_bready,
    m_axi_araddr,
    m_axi_arlen,
    m_axi_arsize,
    m_axi_arburst,
    m_axi_arlock,
    m_axi_arcache,
    m_axi_arprot,
    m_axi_arregion,
    m_axi_arqos,
    m_axi_arvalid,
    m_axi_arready,
    m_axi_rdata,
    m_axi_rresp,
    m_axi_rlast,
    m_axi_rvalid,
    m_axi_rready);
  (* keep = "true" *) input s_axi_aclk;
  (* keep = "true" *) input s_axi_aresetn;
  input [15:0]s_axi_awid;
  input [39:0]s_axi_awaddr;
  input [7:0]s_axi_awlen;
  input [2:0]s_axi_awsize;
  input [1:0]s_axi_awburst;
  input [0:0]s_axi_awlock;
  input [3:0]s_axi_awcache;
  input [2:0]s_axi_awprot;
  input [3:0]s_axi_awregion;
  input [3:0]s_axi_awqos;
  input s_axi_awvalid;
  output s_axi_awready;
  input [127:0]s_axi_wdata;
  input [15:0]s_axi_wstrb;
  input s_axi_wlast;
  input s_axi_wvalid;
  output s_axi_wready;
  output [15:0]s_axi_bid;
  output [1:0]s_axi_bresp;
  output s_axi_bvalid;
  input s_axi_bready;
  input [15:0]s_axi_arid;
  input [39:0]s_axi_araddr;
  input [7:0]s_axi_arlen;
  input [2:0]s_axi_arsize;
  input [1:0]s_axi_arburst;
  input [0:0]s_axi_arlock;
  input [3:0]s_axi_arcache;
  input [2:0]s_axi_arprot;
  input [3:0]s_axi_arregion;
  input [3:0]s_axi_arqos;
  input s_axi_arvalid;
  output s_axi_arready;
  output [15:0]s_axi_rid;
  output [127:0]s_axi_rdata;
  output [1:0]s_axi_rresp;
  output s_axi_rlast;
  output s_axi_rvalid;
  input s_axi_rready;
  (* keep = "true" *) input m_axi_aclk;
  (* keep = "true" *) input m_axi_aresetn;
  output [39:0]m_axi_awaddr;
  output [7:0]m_axi_awlen;
  output [2:0]m_axi_awsize;
  output [1:0]m_axi_awburst;
  output [0:0]m_axi_awlock;
  output [3:0]m_axi_awcache;
  output [2:0]m_axi_awprot;
  output [3:0]m_axi_awregion;
  output [3:0]m_axi_awqos;
  output m_axi_awvalid;
  input m_axi_awready;
  output [31:0]m_axi_wdata;
  output [3:0]m_axi_wstrb;
  output m_axi_wlast;
  output m_axi_wvalid;
  input m_axi_wready;
  input [1:0]m_axi_bresp;
  input m_axi_bvalid;
  output m_axi_bready;
  output [39:0]m_axi_araddr;
  output [7:0]m_axi_arlen;
  output [2:0]m_axi_arsize;
  output [1:0]m_axi_arburst;
  output [0:0]m_axi_arlock;
  output [3:0]m_axi_arcache;
  output [2:0]m_axi_arprot;
  output [3:0]m_axi_arregion;
  output [3:0]m_axi_arqos;
  output m_axi_arvalid;
  input m_axi_arready;
  input [31:0]m_axi_rdata;
  input [1:0]m_axi_rresp;
  input m_axi_rlast;
  input m_axi_rvalid;
  output m_axi_rready;

  (* RTL_KEEP = "true" *) wire m_axi_aclk;
  wire [39:0]m_axi_araddr;
  wire [1:0]m_axi_arburst;
  wire [3:0]m_axi_arcache;
  (* RTL_KEEP = "true" *) wire m_axi_aresetn;
  wire [7:0]m_axi_arlen;
  wire [0:0]m_axi_arlock;
  wire [2:0]m_axi_arprot;
  wire [3:0]m_axi_arqos;
  wire m_axi_arready;
  wire [3:0]m_axi_arregion;
  wire [2:0]m_axi_arsize;
  wire m_axi_arvalid;
  wire [39:0]m_axi_awaddr;
  wire [1:0]m_axi_awburst;
  wire [3:0]m_axi_awcache;
  wire [7:0]m_axi_awlen;
  wire [0:0]m_axi_awlock;
  wire [2:0]m_axi_awprot;
  wire [3:0]m_axi_awqos;
  wire m_axi_awready;
  wire [3:0]m_axi_awregion;
  wire [2:0]m_axi_awsize;
  wire m_axi_awvalid;
  wire m_axi_bready;
  wire [1:0]m_axi_bresp;
  wire m_axi_bvalid;
  wire [31:0]m_axi_rdata;
  wire m_axi_rlast;
  wire m_axi_rready;
  wire [1:0]m_axi_rresp;
  wire m_axi_rvalid;
  wire [31:0]m_axi_wdata;
  wire m_axi_wlast;
  wire m_axi_wready;
  wire [3:0]m_axi_wstrb;
  wire m_axi_wvalid;
  (* RTL_KEEP = "true" *) wire s_axi_aclk;
  wire [39:0]s_axi_araddr;
  wire [1:0]s_axi_arburst;
  wire [3:0]s_axi_arcache;
  (* RTL_KEEP = "true" *) wire s_axi_aresetn;
  wire [15:0]s_axi_arid;
  wire [7:0]s_axi_arlen;
  wire [0:0]s_axi_arlock;
  wire [2:0]s_axi_arprot;
  wire [3:0]s_axi_arqos;
  wire s_axi_arready;
  wire [3:0]s_axi_arregion;
  wire [2:0]s_axi_arsize;
  wire s_axi_arvalid;
  wire [39:0]s_axi_awaddr;
  wire [1:0]s_axi_awburst;
  wire [3:0]s_axi_awcache;
  wire [15:0]s_axi_awid;
  wire [7:0]s_axi_awlen;
  wire [0:0]s_axi_awlock;
  wire [2:0]s_axi_awprot;
  wire [3:0]s_axi_awqos;
  wire s_axi_awready;
  wire [3:0]s_axi_awregion;
  wire [2:0]s_axi_awsize;
  wire s_axi_awvalid;
  wire [15:0]s_axi_bid;
  wire s_axi_bready;
  wire [1:0]s_axi_bresp;
  wire s_axi_bvalid;
  wire [127:0]s_axi_rdata;
  wire [15:0]s_axi_rid;
  wire s_axi_rlast;
  wire s_axi_rready;
  wire [1:0]s_axi_rresp;
  wire s_axi_rvalid;
  wire [127:0]s_axi_wdata;
  wire s_axi_wready;
  wire [15:0]s_axi_wstrb;
  wire s_axi_wvalid;

  design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_axi_downsizer \gen_downsizer.gen_simple_downsizer.axi_downsizer_inst 
       (.CLK(s_axi_aclk),
        .E(s_axi_awready),
        .S_AXI_AREADY_I_reg(s_axi_arready),
        .access_fit_mi_side_q_reg({m_axi_arsize,m_axi_arlen}),
        .command_ongoing_reg(m_axi_awvalid),
        .command_ongoing_reg_0(m_axi_arvalid),
        .din({m_axi_awsize,m_axi_awlen}),
        .\goreg_dm.dout_i_reg[9] (m_axi_wlast),
        .m_axi_araddr(m_axi_araddr),
        .m_axi_arburst(m_axi_arburst),
        .m_axi_arcache(m_axi_arcache),
        .m_axi_arlock(m_axi_arlock),
        .m_axi_arprot(m_axi_arprot),
        .m_axi_arqos(m_axi_arqos),
        .m_axi_arready(m_axi_arready),
        .m_axi_arregion(m_axi_arregion),
        .m_axi_awaddr(m_axi_awaddr),
        .m_axi_awburst(m_axi_awburst),
        .m_axi_awcache(m_axi_awcache),
        .m_axi_awlock(m_axi_awlock),
        .m_axi_awprot(m_axi_awprot),
        .m_axi_awqos(m_axi_awqos),
        .m_axi_awready(m_axi_awready),
        .m_axi_awregion(m_axi_awregion),
        .m_axi_bready(m_axi_bready),
        .m_axi_bresp(m_axi_bresp),
        .m_axi_bvalid(m_axi_bvalid),
        .m_axi_rdata(m_axi_rdata),
        .m_axi_rlast(m_axi_rlast),
        .m_axi_rready(m_axi_rready),
        .m_axi_rresp(m_axi_rresp),
        .m_axi_rvalid(m_axi_rvalid),
        .m_axi_wdata(m_axi_wdata),
        .m_axi_wready(m_axi_wready),
        .m_axi_wstrb(m_axi_wstrb),
        .m_axi_wvalid(m_axi_wvalid),
        .out(s_axi_aresetn),
        .s_axi_araddr(s_axi_araddr),
        .s_axi_arburst(s_axi_arburst),
        .s_axi_arcache(s_axi_arcache),
        .s_axi_arid(s_axi_arid),
        .s_axi_arlen(s_axi_arlen),
        .s_axi_arlock(s_axi_arlock),
        .s_axi_arprot(s_axi_arprot),
        .s_axi_arqos(s_axi_arqos),
        .s_axi_arregion(s_axi_arregion),
        .s_axi_arsize(s_axi_arsize),
        .s_axi_arvalid(s_axi_arvalid),
        .s_axi_awaddr(s_axi_awaddr),
        .s_axi_awburst(s_axi_awburst),
        .s_axi_awcache(s_axi_awcache),
        .s_axi_awid(s_axi_awid),
        .s_axi_awlen(s_axi_awlen),
        .s_axi_awlock(s_axi_awlock),
        .s_axi_awprot(s_axi_awprot),
        .s_axi_awqos(s_axi_awqos),
        .s_axi_awregion(s_axi_awregion),
        .s_axi_awsize(s_axi_awsize),
        .s_axi_awvalid(s_axi_awvalid),
        .s_axi_bid(s_axi_bid),
        .s_axi_bready(s_axi_bready),
        .s_axi_bresp(s_axi_bresp),
        .s_axi_bvalid(s_axi_bvalid),
        .s_axi_rdata(s_axi_rdata),
        .s_axi_rid(s_axi_rid),
        .s_axi_rlast(s_axi_rlast),
        .s_axi_rready(s_axi_rready),
        .s_axi_rresp(s_axi_rresp),
        .s_axi_rvalid(s_axi_rvalid),
        .s_axi_wdata(s_axi_wdata),
        .s_axi_wready(s_axi_wready),
        .s_axi_wstrb(s_axi_wstrb),
        .s_axi_wvalid(s_axi_wvalid));
endmodule

(* ORIG_REF_NAME = "axi_dwidth_converter_v2_1_29_w_downsizer" *) 
module design_1_auto_ds_0_axi_dwidth_converter_v2_1_29_w_downsizer
   (first_mi_word,
    \goreg_dm.dout_i_reg[9] ,
    \goreg_dm.dout_i_reg[12] ,
    \current_word_1_reg[1]_0 ,
    \current_word_1_reg[0]_0 ,
    \current_word_1_reg[2]_0 ,
    Q,
    \current_word_1_reg[3]_0 ,
    SR,
    E,
    CLK,
    \current_word_1_reg[1]_1 ,
    D);
  output first_mi_word;
  output \goreg_dm.dout_i_reg[9] ;
  output \goreg_dm.dout_i_reg[12] ;
  output \current_word_1_reg[1]_0 ;
  output \current_word_1_reg[0]_0 ;
  output \current_word_1_reg[2]_0 ;
  output [2:0]Q;
  output \current_word_1_reg[3]_0 ;
  input [0:0]SR;
  input [0:0]E;
  input CLK;
  input [15:0]\current_word_1_reg[1]_1 ;
  input [3:0]D;

  wire CLK;
  wire [3:0]D;
  wire [0:0]E;
  wire [2:0]Q;
  wire [0:0]SR;
  wire [1:1]current_word_1;
  wire \current_word_1_reg[0]_0 ;
  wire \current_word_1_reg[1]_0 ;
  wire [15:0]\current_word_1_reg[1]_1 ;
  wire \current_word_1_reg[2]_0 ;
  wire \current_word_1_reg[3]_0 ;
  wire first_mi_word;
  wire \goreg_dm.dout_i_reg[12] ;
  wire \goreg_dm.dout_i_reg[9] ;
  wire \length_counter_1[1]_i_1_n_0 ;
  wire \length_counter_1[2]_i_2_n_0 ;
  wire \length_counter_1[3]_i_2_n_0 ;
  wire \length_counter_1[4]_i_2_n_0 ;
  wire \length_counter_1[6]_i_2_n_0 ;
  wire [7:0]length_counter_1_reg;
  wire m_axi_wlast_INST_0_i_1_n_0;
  wire m_axi_wlast_INST_0_i_2_n_0;
  wire [7:0]next_length_counter;

  LUT4 #(
    .INIT(16'hFE02)) 
    \current_word_1[1]_i_2 
       (.I0(current_word_1),
        .I1(\current_word_1_reg[1]_1 [15]),
        .I2(first_mi_word),
        .I3(\current_word_1_reg[1]_1 [12]),
        .O(\current_word_1_reg[1]_0 ));
  LUT4 #(
    .INIT(16'h01FD)) 
    \current_word_1[1]_i_3 
       (.I0(Q[0]),
        .I1(\current_word_1_reg[1]_1 [15]),
        .I2(first_mi_word),
        .I3(\current_word_1_reg[1]_1 [11]),
        .O(\current_word_1_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h000A00F200000000)) 
    \current_word_1[3]_i_2__0 
       (.I0(\current_word_1_reg[1]_0 ),
        .I1(\current_word_1_reg[0]_0 ),
        .I2(\current_word_1_reg[1]_1 [9]),
        .I3(\current_word_1_reg[1]_1 [10]),
        .I4(\current_word_1_reg[1]_1 [8]),
        .I5(\current_word_1_reg[2]_0 ),
        .O(\goreg_dm.dout_i_reg[12] ));
  FDRE \current_word_1_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(D[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE \current_word_1_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(D[1]),
        .Q(current_word_1),
        .R(SR));
  FDRE \current_word_1_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(D[2]),
        .Q(Q[1]),
        .R(SR));
  FDRE \current_word_1_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(D[3]),
        .Q(Q[2]),
        .R(SR));
  FDSE first_word_reg
       (.C(CLK),
        .CE(E),
        .D(\goreg_dm.dout_i_reg[9] ),
        .Q(first_mi_word),
        .S(SR));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT3 #(
    .INIT(8'h1D)) 
    \length_counter_1[0]_i_1 
       (.I0(length_counter_1_reg[0]),
        .I1(first_mi_word),
        .I2(\current_word_1_reg[1]_1 [0]),
        .O(next_length_counter[0]));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT5 #(
    .INIT(32'hCCA533A5)) 
    \length_counter_1[1]_i_1 
       (.I0(length_counter_1_reg[1]),
        .I1(\current_word_1_reg[1]_1 [1]),
        .I2(length_counter_1_reg[0]),
        .I3(first_mi_word),
        .I4(\current_word_1_reg[1]_1 [0]),
        .O(\length_counter_1[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEFA051111FA05)) 
    \length_counter_1[2]_i_1 
       (.I0(\length_counter_1[2]_i_2_n_0 ),
        .I1(\current_word_1_reg[1]_1 [1]),
        .I2(length_counter_1_reg[1]),
        .I3(length_counter_1_reg[2]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [2]),
        .O(next_length_counter[2]));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \length_counter_1[2]_i_2 
       (.I0(\current_word_1_reg[1]_1 [0]),
        .I1(first_mi_word),
        .I2(length_counter_1_reg[0]),
        .O(\length_counter_1[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \length_counter_1[3]_i_1 
       (.I0(length_counter_1_reg[3]),
        .I1(\current_word_1_reg[1]_1 [3]),
        .I2(\current_word_1_reg[1]_1 [2]),
        .I3(first_mi_word),
        .I4(length_counter_1_reg[2]),
        .I5(\length_counter_1[3]_i_2_n_0 ),
        .O(next_length_counter[3]));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT5 #(
    .INIT(32'h00053305)) 
    \length_counter_1[3]_i_2 
       (.I0(length_counter_1_reg[1]),
        .I1(\current_word_1_reg[1]_1 [1]),
        .I2(length_counter_1_reg[0]),
        .I3(first_mi_word),
        .I4(\current_word_1_reg[1]_1 [0]),
        .O(\length_counter_1[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFAFCF305050CF30)) 
    \length_counter_1[4]_i_1 
       (.I0(\current_word_1_reg[1]_1 [3]),
        .I1(length_counter_1_reg[3]),
        .I2(\length_counter_1[4]_i_2_n_0 ),
        .I3(length_counter_1_reg[4]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [4]),
        .O(next_length_counter[4]));
  LUT6 #(
    .INIT(64'h0000000511110005)) 
    \length_counter_1[4]_i_2 
       (.I0(\length_counter_1[2]_i_2_n_0 ),
        .I1(\current_word_1_reg[1]_1 [1]),
        .I2(length_counter_1_reg[1]),
        .I3(length_counter_1_reg[2]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [2]),
        .O(\length_counter_1[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFAFCF305050CF30)) 
    \length_counter_1[5]_i_1 
       (.I0(\current_word_1_reg[1]_1 [4]),
        .I1(length_counter_1_reg[4]),
        .I2(m_axi_wlast_INST_0_i_2_n_0),
        .I3(length_counter_1_reg[5]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [5]),
        .O(next_length_counter[5]));
  LUT6 #(
    .INIT(64'hAFAFCF305050CF30)) 
    \length_counter_1[6]_i_1 
       (.I0(\current_word_1_reg[1]_1 [5]),
        .I1(length_counter_1_reg[5]),
        .I2(\length_counter_1[6]_i_2_n_0 ),
        .I3(length_counter_1_reg[6]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [6]),
        .O(next_length_counter[6]));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    \length_counter_1[6]_i_2 
       (.I0(\current_word_1_reg[1]_1 [3]),
        .I1(length_counter_1_reg[3]),
        .I2(\length_counter_1[4]_i_2_n_0 ),
        .I3(length_counter_1_reg[4]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [4]),
        .O(\length_counter_1[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFAFCF305050CF30)) 
    \length_counter_1[7]_i_1 
       (.I0(\current_word_1_reg[1]_1 [6]),
        .I1(length_counter_1_reg[6]),
        .I2(m_axi_wlast_INST_0_i_1_n_0),
        .I3(length_counter_1_reg[7]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [7]),
        .O(next_length_counter[7]));
  FDRE \length_counter_1_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[0]),
        .Q(length_counter_1_reg[0]),
        .R(SR));
  FDRE \length_counter_1_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\length_counter_1[1]_i_1_n_0 ),
        .Q(length_counter_1_reg[1]),
        .R(SR));
  FDRE \length_counter_1_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[2]),
        .Q(length_counter_1_reg[2]),
        .R(SR));
  FDRE \length_counter_1_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[3]),
        .Q(length_counter_1_reg[3]),
        .R(SR));
  FDRE \length_counter_1_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[4]),
        .Q(length_counter_1_reg[4]),
        .R(SR));
  FDRE \length_counter_1_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[5]),
        .Q(length_counter_1_reg[5]),
        .R(SR));
  FDRE \length_counter_1_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[6]),
        .Q(length_counter_1_reg[6]),
        .R(SR));
  FDRE \length_counter_1_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(next_length_counter[7]),
        .Q(length_counter_1_reg[7]),
        .R(SR));
  LUT4 #(
    .INIT(16'hFE02)) 
    \m_axi_wdata[31]_INST_0_i_4 
       (.I0(Q[1]),
        .I1(\current_word_1_reg[1]_1 [15]),
        .I2(first_mi_word),
        .I3(\current_word_1_reg[1]_1 [13]),
        .O(\current_word_1_reg[2]_0 ));
  LUT4 #(
    .INIT(16'h01FD)) 
    \m_axi_wdata[31]_INST_0_i_5 
       (.I0(Q[2]),
        .I1(\current_word_1_reg[1]_1 [15]),
        .I2(first_mi_word),
        .I3(\current_word_1_reg[1]_1 [14]),
        .O(\current_word_1_reg[3]_0 ));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    m_axi_wlast_INST_0
       (.I0(\current_word_1_reg[1]_1 [6]),
        .I1(length_counter_1_reg[6]),
        .I2(m_axi_wlast_INST_0_i_1_n_0),
        .I3(length_counter_1_reg[7]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [7]),
        .O(\goreg_dm.dout_i_reg[9] ));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    m_axi_wlast_INST_0_i_1
       (.I0(\current_word_1_reg[1]_1 [4]),
        .I1(length_counter_1_reg[4]),
        .I2(m_axi_wlast_INST_0_i_2_n_0),
        .I3(length_counter_1_reg[5]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [5]),
        .O(m_axi_wlast_INST_0_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000003050500030)) 
    m_axi_wlast_INST_0_i_2
       (.I0(\current_word_1_reg[1]_1 [2]),
        .I1(length_counter_1_reg[2]),
        .I2(\length_counter_1[3]_i_2_n_0 ),
        .I3(length_counter_1_reg[3]),
        .I4(first_mi_word),
        .I5(\current_word_1_reg[1]_1 [3]),
        .O(m_axi_wlast_INST_0_i_2_n_0));
endmodule

(* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) 
(* INV_DEF_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_cdc_async_rst" *) (* RST_ACTIVE_HIGH = "1" *) 
(* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) 
(* keep_hierarchy = "true" *) (* xpm_cdc = "ASYNC_RST" *) 
module design_1_auto_ds_0_xpm_cdc_async_rst
   (src_arst,
    dest_clk,
    dest_arst);
  input src_arst;
  input dest_clk;
  output dest_arst;

  (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "ASYNC_RST" *) wire [1:0]arststages_ff;
  wire dest_clk;
  wire src_arst;

  assign dest_arst = arststages_ff[1];
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "ASYNC_RST" *) 
  FDPE #(
    .INIT(1'b0)) 
    \arststages_ff_reg[0] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(1'b0),
        .PRE(src_arst),
        .Q(arststages_ff[0]));
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "ASYNC_RST" *) 
  FDPE #(
    .INIT(1'b0)) 
    \arststages_ff_reg[1] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(arststages_ff[0]),
        .PRE(src_arst),
        .Q(arststages_ff[1]));
endmodule

(* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) 
(* INV_DEF_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_cdc_async_rst" *) (* RST_ACTIVE_HIGH = "1" *) 
(* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) 
(* keep_hierarchy = "true" *) (* xpm_cdc = "ASYNC_RST" *) 
module design_1_auto_ds_0_xpm_cdc_async_rst__3
   (src_arst,
    dest_clk,
    dest_arst);
  input src_arst;
  input dest_clk;
  output dest_arst;

  (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "ASYNC_RST" *) wire [1:0]arststages_ff;
  wire dest_clk;
  wire src_arst;

  assign dest_arst = arststages_ff[1];
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "ASYNC_RST" *) 
  FDPE #(
    .INIT(1'b0)) 
    \arststages_ff_reg[0] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(1'b0),
        .PRE(src_arst),
        .Q(arststages_ff[0]));
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "ASYNC_RST" *) 
  FDPE #(
    .INIT(1'b0)) 
    \arststages_ff_reg[1] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(arststages_ff[0]),
        .PRE(src_arst),
        .Q(arststages_ff[1]));
endmodule

(* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "0" *) 
(* INV_DEF_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_cdc_async_rst" *) (* RST_ACTIVE_HIGH = "1" *) 
(* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* is_du_within_envelope = "true" *) 
(* keep_hierarchy = "true" *) (* xpm_cdc = "ASYNC_RST" *) 
module design_1_auto_ds_0_xpm_cdc_async_rst__4
   (src_arst,
    dest_clk,
    dest_arst);
  input src_arst;
  input dest_clk;
  output dest_arst;

  (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "ASYNC_RST" *) wire [1:0]arststages_ff;
  wire dest_clk;
  wire src_arst;

  assign dest_arst = arststages_ff[1];
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "ASYNC_RST" *) 
  FDPE #(
    .INIT(1'b0)) 
    \arststages_ff_reg[0] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(1'b0),
        .PRE(src_arst),
        .Q(arststages_ff[0]));
  (* ASYNC_REG *) 
  (* KEEP = "true" *) 
  (* XPM_CDC = "ASYNC_RST" *) 
  FDPE #(
    .INIT(1'b0)) 
    \arststages_ff_reg[1] 
       (.C(dest_clk),
        .CE(1'b1),
        .D(arststages_ff[0]),
        .PRE(src_arst),
        .Q(arststages_ff[1]));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2023.2"
`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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oD/8serz9uvKt9uVuyMIE6oOFFScZR6q2wQk1d1Qzq717+8yPCwgBT9HIhfJIHLujHt+cA2l2L5t
tux9aNBdVKkk1MHv7yY=

`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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KOC8JtqORVWmhq47cpQ=

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2022_10", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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VyT7JTUW5P/rcLgzkfyKToozq36lEkXd6VSaLg==

`pragma protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
T4EV2kKcg5a7rlvEGr4AG3uvv0JzSoc0NQb9aIeE2gsKGq0oLel4q0oZ7eO6He8noW5KEowgkY0O
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`pragma protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`pragma protect key_block
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`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 239840)
`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
